Method and system for reducing inter-layer capacitance in...

Details Method and system for reducing inter-layer capacitance in... Method and system for reducing inter-layer capacitance in...

2008-07-08

2008-07-08

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S012000, C438S017000

Reexamination Certificate

active

10991107

ABSTRACT:
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

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Hierarchical Dummy Fill for Process Uniformity; Yu Chen, Andrew B. Kahng, Gabriel Robins and Alexander Zelikovsky; Computer Science Department, UCLA, Los Angeles, CA 90095-1596; UCSD CSE and ECE Departments, La Jolla, CA 92093-0114; Department of Computer Science, University of Virginia, Charlottesville, VA 22903-2442; Department of Computer Science, Georgia State University, Atlanta, GA 30303.
Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Density Equalization; Brian Lee, Duane S. Boning, Dale L. Hetherington and David J. Stein; Massachusetts Institute of Technology, Cambridge, MA, Sandia National Laboratories, Albuquerque, NM; Mar. 2000.

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