Method and system for reducing inter-layer capacitance in...

Details Method and system for reducing inter-layer capacitance in... Method and system for reducing inter-layer capacitance in...

2008-07-08

2008-07-08

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S012000, C438S017000

Reexamination Certificate

active

07396760

ABSTRACT:
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

REFERENCES:
patent: 5763955 (1998-06-01), Findley et al.
patent: 6751785 (2004-06-01), Oh
patent: 6998653 (2006-02-01), Higuchi
patent: 7015582 (2006-03-01), Landis
patent: 7089522 (2006-08-01), Tan et al.
patent: 7152215 (2006-12-01), Smith et al.
patent: 7188321 (2007-03-01), Wong et al.
patent: 2002/0190382 (2002-12-01), Kouno et al.
patent: 2005/0186751 (2005-08-01), Beach et al.
Hierarchical Dummy Fill for Process Uniformity; Yu Chen, Andrew B. Kahng, Gabriel Robins and Alexander Zelikovsky; Computer Science Department, UCLA, Los Angeles, CA 90095-1596; UCSD CSE and ECE Departments, La Jolla, CA 92093-0114; Department of Computer Science, University of Virginia, Charlottesville, VA 22903-2442; Department of Computer Science, Georgia State University, Atlanta, GA 30303.
Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Density Equalization; Brian Lee, Duane S. Boning, Dale L. Hetherington and David J. Stein; Massachusetts Institute of Technology, Cambridge, MA, Sandia National Laboratories, Albuquerque, NM; Mar. 2000.

Affiliated with

Also associated with

Rating

Method and system for reducing inter-layer capacitance in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for reducing inter-layer capacitance in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for reducing inter-layer capacitance in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2759185