Method and system for reduced column redundancy using a dual col

Details Method and system for reduced column redundancy using a dual col Method and system for reduced column redundancy using a dual col

1996-07-22

1998-03-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, 3652301, G11C 1300

Patent

active

057320306

ABSTRACT:
A semiconductor memory device (10) includes a plurality of row address inputs (RA0-RA8), and a plurality of column address input (CA0-CA8) lines. A plurality of main memory subarrays (122) include a plurality of memory cells (122). A plurality of redundant memory arrays are associated with the main memory arrays. Column redundancy circuitry (68) receives column addresses (CA3-CA7) for determining if a match occurs between the received column addresses and the stored redundant column information.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4392211 (1983-07-01), Nakano et al.
patent: 5060197 (1991-10-01), Park et al.
patent: 5270975 (1993-12-01), McAdams
patent: 5576633 (1996-11-01), Rountree
"Laser Programmable Redundancy and Yield Improvement in a 64 K Dram"by Robert T. Smith, James D. Chlipala, John F.M. Bindels, Roy G. Nelson, Frederick H. Fischer and Thomas F. Mantz, 1981 IEEE.

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