Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-12-29
2002-11-05
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S033000, C710S038000
Reexamination Certificate
active
06477625
ABSTRACT:
BACKGROUND OF THE PRESENT INVENTION
1. Field of the Invention
The present invention relates to a method for reading a memory, particularly a non-volatile memory. More particularly, the invention relates to a particular read protocol.
2. Description of the Related Art
It is known that in a conventional memory, particularly of the non-volatile type, a read method that is typically used is a so-called random method, in which word lines and bit lines of the memory are selected randomly and independently. The random method entails read times which are the sum of a sequence of elementary events that can be summarized substantially as follows: (1) selection of word line and bit line paths, (2) bit line pre-charge activity, (3) data evaluation, and (4) propagation for the transfer of the data to an output buffer and transition time of the output buffer.
The total read time of the memory, given by the sum of the times of the individual operations listed above, depends not only on the size of the memory and on its architecture, but also on the type of devices that are present in the memory, i.e., on the technology used.
The advantages of a conventional architecture and read protocol reside in the fact that the architecture provided is simple (minimal-number memory structure), allows easy timing (because the read cycles are all identical), provides maximum efficiency for redundancy structures, and has significantly low consumption of power since the current-absorbing circuits are kept to the smallest possible number. However, the limitation of the conventional architecture and read protocol is indeed the speed at which data can be read (i.e., read speed), which becomes highly important in large memories.
One possible approach for improving the read speed is the use of a page-type read mode, in which a plurality of words in parallel, for example eight, are read during a first cycle. The content of the read operation is stored in a suitable register and the register portion related to the chosen word in a packet of read words is displayed externally (i.e., visible to circuitry external to the memory).
By operating in the page-type read mode, it is possible to scan the words contained in the packet of read words in a significantly shorter time than with a random-type read. However, the first read cycle remains tied to the time required by a random-type read solution.
Page-type read mode reading is in any case affected by some drawbacks, such as: (1) a large number of read circuits (e.g., if eight words in parallel are read and each word contains eight bits, sixty-four sense amplifiers are required); (2) a high current absorption during parallel reading; (3) a need for word registers; (4) a need for register decoding; (5) a reduction in the effectiveness of the redundancy structures, meaning that one line at a time can be replaced with a redundancy line, but in the case of a multiple read, the possibilities of a fault on a line increase, while there is still only one redundancy line available; and (6) a read protocol which provides for a dual cycle time to include random and page read modes.
FIG. 1
illustrates a conventional memory read protocol showing the characteristic of fully stimulating all the selection paths within the memory device from the start of each read and then continuing with the development of the read cycle until external transfer of the read data is achieved. The signal designated by CE indicates chip enabling, while the signal designated by OE indicates data output enabling. The reference signs A
0
-A
15
designate the address transitions and the read cycle time t_cy is defined between one transition and the next.
Limitation of the data Q
0
-Q
15
occurs at a time t_CE after the falling edge of the signal CE, at a time t_OE after the falling edge of the signal OE, and at a time t_ADD after the address transition of the addresses A
0
-A
15
. The known read cycle timing also entails the drawback that reading occurs exclusively when a new read cycle begins, since the memory location to which the next read activity is to be targeted is otherwise unknown. The known read cycle timing ensures that every read operation requires a long time, since the read cycle time is, as mentioned, the sum of all the elementary events.
SUMMARY OF THE INVENTION
A more complete appreciation of the present invention and the scope thereof can be obtained from the accompanying drawings which are briefly summarized below, the following detailed description of the presently-preferred embodiments of the invention, and the appended claims.
The present invention includes a method for reading a memory by applying control signals. The control signals include a memory enable signal, a visibility signal, and a read signal. The visibility signal provides the allowability of the memory to utilize an externally generated address that points to a memory location internal to the memory. By applying the control signals to the memory, the memory is configured into any of a plurality of cycles associated with reading the memory. The different cycles include: random read, pipeline-type random read, sequential read, and suspend and wait cycles. Depending upon the configured cycle, data that coincides with the externally generated address is selectively emitted and/or outputted from the memory.
REFERENCES:
patent: 5452261 (1995-09-01), Chung et al.
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5675549 (1997-10-01), Ong et al.
patent: 5745409 (1998-04-01), Wong et al.
patent: 0849739 (1998-06-01), None
patent: 0854485 (1998-07-01), None
Zwie Amitai et al: “Burst Mode Memories Improve Cache Design” Electro International Conference Record, vol. 16, No. 2, Apr. 16, 1991, pp. 279-282, XP000287207.
Fontana Marco
Pascucci Luigi
Jenkins & Gilchrist
Peikari B. James
STMelectronics S.r.l.
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