Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-18
2003-12-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C327S541000, C327S540000
Reexamination Certificate
active
06665843
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of design automation and computer-aided design (CAD) of integrated circuits, and more particularly, to a method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by the power supply network drops below a predetermined voltage level when a predetermined number of electrical elements switch simultaneously.
DESCRIPTION OF RELATED ART
Today CMOS (Complementary Metal Oxide Semiconductor) circuit technology and its application to synchronous switching digital VLSI (Very Large Scale Integration) that operates at high frequencies and which shows significant current fluctuations imposes serious constraints on the associated power supplies. The reason lies in the semiconductor fabrication. CMOS circuit technology which uses a combination of n and p-doped semiconductors to achieve low power dissipation. Any path through a gate where current flows includes both kinds of transistors (i.e., n and p-type). Since only one type turns on to a stable state, there is hardly any static power dissipation. However, current flows when the gate switches, which normally occurs when charging the parasitic capacitances.
Current fluctuations typically generate noise voltages, i.e., unintentional variations of the voltage level. Because of such fluctuations, the supply voltage level is prone to drop even below a predetermined voltage level necessary for the faultless operation of the circuits comprising the chip or module, which jeopardizes the operation of the entire system. Therefore, one of the major challenges in modern circuit design is to design a reliable power supply system, i.e., one that provides a voltage supply level that stays within a predefined range even under worst case conditions. Thus, the power supply is required to display a minimum amount of noise even when all the gates forming the logic or memory switch simultaneously.
A conventional approach is to built a power supply network which maintains the lowest possible impedance, from DC level up to its highest operational frequency. In such a system, power supply noise is at minimum. To achieve this goal, the designer provides decoupling capacitors, each generating a local capacitance along the power path from the primary power source down to the switching circuits. The closer to the switching circuit high frequency capacitors, i.e., those showing a good high frequency response, the better the provision for high speed current changes. Ultimately, the power supply decoupling capacitors are best distributed at the chip level among the switching circuits. However, tools to simulate the on-chip power distribution are not commonplace today and are very complex. Furthermore, it is hardly possible to use them interactively during chip physical design, because of their complexity.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and a system for analyzing the dynamic behavior of an electrical circuit as part of an integrated circuit to determine whether a voltage level provided by the power supplies drops below a predetermined level during operation of the electrical circuit.
It is another object to provide a method and a system for analyzing the dynamic behavior of the electrical circuit to determine that the voltage level provided by the power supply network drops below the predetermined voltage level when a predetermined number of electrical elements switch simultaneously.
BRIEF SUMMARY OF THE INVENTION
The foregoing and other objects are achieved by a method and a system for analyzing the dynamic behavior of electrical circuits as part of an integrated circuit, wherein each electrical circuit includes a plurality of electrical elements and a power supply system. The power supply system is formed by an external voltage source and by a plurality of electrical connections for providing a predetermined supply voltage level U
0
to each electrical element. An analysis determines whether the voltage level at any of the electrical elements drops below a predetermined voltage level when a certain number of electrical elements switch simultaneously. In order to calculate a worst case, it is considered that all electrical elements switch from one state into another at the same time.
In a first step, a design data set that represents the technical specifications of the electrical circuit or the integrated circuit, is read in order to extract the location and the value of the switching and non-switching capacitance C
s
, C
0
. Additionally, a circuit and technology specified propagation speed &ngr; is provided. In the next step, a length is determined to specify the size of a portion of a circuit area upon which the electrical circuit is formed. Thereafter, the circuit area is divided in a plurality of partitions of a specified size, and the switching capacitance C
s
and the non-switching capacitance C
0
are separately summarized for each portion. Then, the voltage level drop &Dgr;U is individually calculated for each partition. Finally, the calculated voltage level drop &Dgr;U is displayed in relation to the respective partition.
The method of the present invention can be used for on-chip power supply network evaluation. It was found to be sufficiently efficient for early use in the chip development process and the chip physical design phase. Since the method and system measures the power supply integrity, i.e., whether the power supply operation is unimpaired by the circuit operation, it allows optimize the chip layout and power supply decoupling capacitors.
The behavior of a power supply system being a part of an electrical circuit subjected to analysis, as described above, is conditioned by many different electrical values, such as the non-inductive resistance, the capacity reactance and the inductance. However, typically, the power supply networks in question are mainly inductance dominated, i.e., the influence of the inductance on the system behavior is comparably larger so that the other electrical values may even be neglected for the purpose of the analysis, in accordance to the present invention. Every electrical element, being part of the analyzed electrical circuit, provides a certain capacitance. For the analysis, according to the present invention, the capacitance of each electrical element is divided in two different types. The first type is referred to as switching capacitance C
s
, i.e., a capacitance which has to be charged whenever the respective electrical element changes its state or switches. The second type is a non-switching capacitance C
0
which in not effected by changing the state of the electrical element nor by its switching. The non-switching capacitance C
0
, however, keeps some electrical charge which may be supplied to the power supply network.
Charging the switching capacitance C
s
of an electrical element during switching is a major physical effect which needs external power supply support. Due to the high switching speed, the inductance dominated power supply path mainly controls the behavior of the voltage level provided by the power supply network to the switching electrical elements. Because of this, an external power supply cannot instantly provide sufficient electrical charge demanded by an electrical element in order to charge the switching capacitance C
s
. Instead, the electrical charge needed to charge the switching capacitance C
s
is at first taken from the non-switching capacitance C
0
being situated very closely in relation to the switching location. Hence, only a fraction of the entire non-switching capacitance C
0
is available to provide the electrical charge that is needed for a switching event.
Using the law of charge conservation, the initial voltage collapse or voltage level drop DU of the nominal power supply voltage level U
0
can generally be calculated as follows:
Q
0
=
C
0
·
U
0
=
(
C
0
+
C
S
)
·
(
U
0
-
Δ
U
)
→
Δ
U
=
C
S
C
Frech Roland
Huber Andreas
Klink Erich
Supper Jochen
Dimyan Magid Y
International Business Machines - Corporation
Schnurmann H. Daniel
Siek Vuthe
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