Method and system for providing universal memory bus and module

Details Method and system for providing universal memory bus and module Method and system for providing universal memory bus and module

1999-10-01

2002-10-29

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S101000

Reexamination Certificate

active

06473831

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory bus architecture, and in particular to a memory bus capable of interfacing to memory modules which hold a multiplicity of different types of memory devices.
BACKGROUND OF THE INVENTION
Many types of memory exist in a modem computer system including static RAM, dynamic RAM, programmable FLASH, and magnetic disks. Over the years the physical locations of these memories have become separated due to various electrical and physical differences between the memory types. Helped by the increasing miniaturization of memories, it is now become possible to combine these memories on a few subassemblies or modules.
However, due to a number of factors, previous attempts at producing memory modules which incorporate different types of memory on the same module have failed to find widespread acceptance. It is the purpose of this invention to describe the necessary characteristics of a universal memory bus that allows properly constituted memory modules to incorporate a wide variety of memory types. the 1960's, DRAM memory modules were introduced by Wang Computer and subsequently by many other manufacturers. Many benefits resulted from placing multiple DRAM memory chips on a removable memory module instead of directly on the same printed circuit board (PCB) as the CPU. These include saving space on the CPU board, efficiency of manufacturing and testing, and allowing the user of the computer system to easily upgrade the amount of DRAM memory in his system.
Because of the benefits just described, DRAM memory modules are now the standard means by which DRAM is included in a computer system. Also, because it is recognized that other types of memory besides DRAM memory can benefit from placement on similar modules, memory module standards can include specifications for other types of memory. The standards for the most common memory modules are done by an international committee called JEDEC and are defined in JEDEC JESD 21 C Solid State Memory Standards. The following discussion looks at a specific JEDEC 100 pin DIMM Standard (JEDEC Standard No.21-C 4.4.8) in order to illustrate one means by which different types of memory can be placed in the same physical form factor.
The JEDEC 100 pin DIMM standard has assigned pins for three types of memory devices; namely DRAM, SDRAM, and ROM.
FIG. 1
of this patent illustrates how two 100 pin DIMM modules
14
and
16
with different memory types can be placed in the same computer system
10
. The connection scheme for the two 100 pin DIMM modules
14
and
16
shown in
FIG. 1
avoids signal conflicts between different types of memory by restricting each individual module
14
and
16
to only one type of memory device per memory module.
However, it is desirable to allow a memory bus to be connected to a suitable memory module that contains a variety of types of memory devices. The desired memory bus
12
′ and module
18
are shown in FIG.
2
. To understand the problems associated with the memory module scheme of
FIG. 2
, three new terms will be introduced; namely, “memory element”, “memory use mode”, and “memory signal set”. The term “memory element” refers to either a memory chip or memory module. The definition of the terms “memory use mode” and “memory signal set” will be made clear in the subsequent paragraphs.
All the signals of a memory element can be divided in four signal groups; power, control, address, and data. The power lines provide the energy for the chip to function. The address lines are used to access a specific location of memory. The data lines provide the information at the addressed locations. And the control lines provide the direction and control of the data transfer.
Now comes the central question with respect to producing a workable memory module with multiple types of memory. If we include a complete set of power, control, address, and data signals in the connector of our universal memory element, would we not have a working multi-memory element?
End The answer to the above question is no; because the signal definition for any given pin on a memory element can be different depending the actual memory use mode of the memory element.
An example of more than one use for a particular memory pin is described herein below. Parallel EPROM/FLASH memories typically hold the boot code for standard Personal Computers. These memories are used because they retain their programmed data when powered down yet provided fairly fast access to this same data when powered up. The signals of a parallel EPROM/FLASH memory include an address line described as A
9
. When such a memory is normally used in a computer system, the address line A
9
is wired like all the other address lines of the device and is connected to line A
9
of the local CPU
102
bus.
FIG. 3A
illustrates the connection of the address line A
9
to line A
9
of the CPU
102
.
However, when the EPROM/FLASH is programmed with the boot code for the CPU, by convention, a special super voltage is placed on A
9
along with other suitable signals in order to allow a PROM programmer (a test instrument) to identify the actual type of EPROM being programmed.
FIG. 3B
illustrates the connection of the address line A
9
of the EPROM/FLASH device
104
to a super voltage. The identification number read is usually a four byte hexadecimal number and is called the device's silicon signature. Thus we see that the signal definition of A
9
for the typical boot EPROM/FLASH device
104
depends upon whether the chip is in the programming mode or in the normal memory access mode.
When both the EPROM/FLASH device
104
and a non-programmable memory such as a DRAM are placed on the same memory card, a programming problem will occur. Namely, if A
9
of the programmable memory is connected to A
9
of the DRAM, we will not be able to place a super voltage on A
9
to read the silicon signature of the EPROM/Flash us memory because it will harm the DRAM. If on the other hand, we keep them separate, the two different memory devices will not share the same signals on the memory bus.
Other common parallel EPROM and FLASH signals lines which often have super voltage values (e.g. 12 volts) applied during the programming mode include the memory chip select, output enable, write enable, and the reset/power down lines. For EPROM's, these super voltages often need to be applied for programming of the main memory array. In FLASH devices, these signals are typically needed to program special sections of the device for protection of sectors from regular programming which are commonly referred to as “boot block sectors”.
All of the groups of signals required for the various modes of programming form a group of “programming signal sets” for the “program use mode”. An accommodation for many of the super voltages required for the programming signal sets is typically absent from current memory module design. Only the intended memory use mode of the memory device is considered when selecting the actual signals that constitute the signal lines of the memory module. This is precisely the case with the JEDEC 100 pin DIMM standard reviewed earlier.
When all of the memory devices on a memory module are of the same device type, this will normally not present a problem in terms of programming. However, in the case of a Ids mixed memory type module, the inability to connect the correct programming signal sets will prevent full testing and programming of the programmable device on a module.
It is important to note that all memory elements including non-programmable memory elements have at least two different memory use modes; namely, a group of test modes and also the normal intended memory read and write access modes. These latter as modes will be referred to as the “normal use modes”. Since the signal sets required for testing non-programmable devices may also conflict with the signal sets required for the normal use mode, the mixing of different types of memory on any give module may present real conflicts due to differences in the test modes

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