Method and system for providing spin transfer tunneling...

Details Method and system for providing spin transfer tunneling... Method and system for providing spin transfer tunneling...

2007-06-15

2010-06-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S148000, C365S072000, C977S935000

Reexamination Certificate

active

07742328

ABSTRACT:
A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

REFERENCES:
patent: 6541792 (2003-04-01), Tran et al.
patent: 6940747 (2005-09-01), Sharma et al.
patent: 7009877 (2006-03-01), Huai et al.
patent: 2003/0184919 (2003-10-01), Lin et al.
patent: 2005/0061658 (2005-03-01), Lin et al.
patent: 2005/0148137 (2005-07-01), Brask et al.
patent: 2005/0174702 (2005-08-01), Gill
patent: 2005/0199913 (2005-09-01), Hofmann et al.
patent: 2006/0141640 (2006-06-01), Huai et al.
patent: 2007/0097730 (2007-05-01), Chen et al.
PCT International Search Report and Written Opinion of the International Searching Authority, issued Sep. 10, 2008, application No. PCT/US08-66857.
H.-S.P. Wong, “Beyond the conventional transistor”, IBM Journal of Research and Development, vol. 46, No. 2/3, Mar./May 2002.
Thomas Skotnicki, et al., “The End of CMOS Scaling”, IEEE Circuits & Devices Magazine, Jan./Feb. 2005.
Yang-Kyu Choi, et al., “Sub-20nm CMOS FinFET Technologies”, IEDM Technical Digest 2001.
Xuejue Huang, et al., “Sub-50 nm P-Channel FinFET”, IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001.
Digh Hisamoto, et al., “A Folded-channel MOSFET for Deep-sub-tenth Micron Era”, IEDM Technical Digest 1998.
Digh Hisamoto, et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000.
Toshiki Saito, et al., “Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs”, IEICE Trans. Electron, vol. E85-C, No. 5, May 2002.
Digh Hisamoto, et al., A Fully Depleted Lean-Channel Transistor (DELTA)—A Novel Vertical Ultrathin SOI MOSFET, IEEE Electron Device Letters, vol. 11, No. 1, Jan. 1990.
PCT International Preliminary Report on Patentability, issued Dec. 17, 2009, application No. PCT/US2008/066857.

Affiliated with

Also associated with

Rating

Method and system for providing spin transfer tunneling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for providing spin transfer tunneling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for providing spin transfer tunneling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4200113