Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2003-07-09
2008-03-25
Perez-Gutierrez, Rafael (Department: 2617)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C714S001000, C370S359000
Reexamination Certificate
active
07350012
ABSTRACT:
A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.
REFERENCES:
patent: 5862403 (1999-01-01), Kanai et al.
patent: 5925120 (1999-07-01), Arp et al.
patent: 6038288 (2000-03-01), Thomas et al.
patent: 6052795 (2000-04-01), Murotani et al.
patent: 6195351 (2001-02-01), Hiscock et al.
patent: 6295575 (2001-09-01), Blumenau et al.
patent: 6343067 (2002-01-01), Drottar et al.
patent: 6661786 (2003-12-01), Abbiate et al.
patent: 6674971 (2004-01-01), Boggess et al.
patent: 6691185 (2004-02-01), Avery
patent: 6865157 (2005-03-01), Scott et al.
patent: 6895528 (2005-05-01), Cantwell et al.
patent: 7062591 (2006-06-01), Pecone
patent: 2002/0071386 (2002-06-01), Gronke
patent: 2002/0080723 (2002-06-01), Hoch et al.
patent: 2002/0191547 (2002-12-01), Akyol et al.
patent: 2003/0090997 (2003-05-01), Lindstrom
patent: 2003/0204770 (2003-10-01), Bergsten
patent: 2003/0236920 (2003-12-01), Harris et al.
patent: 2004/0168008 (2004-08-01), Benson et al.
Gagnon Stephane
Menasce Victor
Kasraian Allahyar
Perez-Gutierrez Rafael
Tundra Semiconductor Corporation
LandOfFree
Method and system for providing fault tolerance in a network does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for providing fault tolerance in a network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for providing fault tolerance in a network will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3964725