Method and system for providing bit error rate characterization

Details Method and system for providing bit error rate characterization Method and system for providing bit error rate characterization

2011-06-14

2011-06-14

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S712000

Reexamination Certificate

active

07962806

ABSTRACT:
An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to whether a link failure condition exists at a port on an Ethernet switch.

REFERENCES:
patent: 4347600 (1982-08-01), Abbott et al.
patent: 4376999 (1983-03-01), Abbott et al.
patent: 4710924 (1987-12-01), Chum
patent: 6094737 (2000-07-01), Fukasawa
patent: 6550029 (2003-04-01), Bailey et al.
patent: 7079612 (2006-07-01), Tarng
patent: 7624323 (2009-11-01), Casillas et al.

Affiliated with

Also associated with

Rating

Method and system for providing bit error rate characterization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for providing bit error rate characterization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for providing bit error rate characterization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2642257