Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-02-26
2001-07-24
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S141000, C711S145000, C711S155000, C712S028000
Reexamination Certificate
active
06266743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and system for data processing in general, and in particular to a method and system for providing an eviction protocol for a sparse directory. Still more particularly, the present invention relates to a method and system for evicting a cache line from a sparse directory within a non-uniform memory access computer system.
2. Description of the Prior Art
It is well-known in the computer arts that greater computer system performance can be achieved by combining the processing power of several individual processors to form a multiprocessor (MP) computer system. MP computer systems can be designed with a number of different topologies, depending on the performance requirements of a particular application. A symmetric multiprocessor (SMP) configuration, for example, is one of the simpler MP computer system topologies that are commonly used, in which resources such as a system memory are shared by multiple processors. The topology name “symmetric” stems from the fact that all processors within an SMP computer system have symmetric access to all resources within the system.
Although the SMP topology permits the use of relatively simple inter-processor communication and data sharing protocols, the SMP topology overall has a limited scalability and bandwidth, especially at the system memory level as the system scale increases. As a result, another MP computer system topology known as non-uniform memory access (NUMA) has emerged as an alternative design that addresses many of the limitations of the SMP topology, at the expense of some additional complexity.
A typical NUMA computer system includes a number of interconnected nodes. Each node includes at least one processor and a local “system” memory. The NUMA topology name stems from the fact that a processor has lower access latency with respect to data stored in the system memory at its local node than with respect to data stored in the system memory at a remote node. NUMA computer systems can be further classified as either non-cache coherent or cache coherent, depending on whether or not data coherency is maintained among caches in different nodes. The NUMA topology addresses the scalability limitations of the conventional SMP topology by implementing each node within a NUMA computer system as a smaller SMP system. Thus, the shared components within each node can be optimized for use by only a few processors, while the overall system benefits from the availability of larger scale parallelism with relatively low latency.
There are several problems associated with the development of an eviction protocol for a sparse directory within a NUMA computer system. The first problem arises from the management of an entry that is selected to be evicted, the second problem arises from the generation of remote transactions that are used to cause the eviction to occur, and the third problem arises from the generation of a transaction to cause the actual writeback of data to the local memory. Consequently, it would be desirable to provide an improved method for evicting a cache line from a sparse directory within a NUMA computer system.
SUMMARY OF THE INVENTION
In accordance with the method and system of the present invention, a NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request for evicting an entry from a sparse directory, an non-intervention writeback request is sent to a node having the modified cache line when the entry is associated with a modified cache line. After the data from the modified cache line has been written back to a local system memory of the node, the entry can then be evicted from the sparse directory. If the entry is associated with a shared line, an invalidation request is sent to all nodes that the directory entry indicates may hold a copy of the line. Once all invalidations have been acknowledged, the entry can be evicted from the sparse directory.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4775955 (1988-10-01), Liu
patent: 4885680 (1989-12-01), Anthony et al.
patent: 5313609 (1994-05-01), Baylor et al.
patent: 5606686 (1997-02-01), Tarui et al.
patent: 5680576 (1997-10-01), Laudon
patent: 5684977 (1997-11-01), Van Loo et al.
patent: 5893144 (1999-04-01), Wood et al.
patent: 6085295 (2000-07-01), Ekanadham et al.
patent: 6108764 (2000-08-01), Baumgartner et al.
T.D. Lovett et al., “Numa-Q: An Sci-Based Enterprise Server,” Sequent Computer Systems, 1996.
Carpenter Gary Dale
Dean Mark Edward
Glasco David Brian
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Pharm Vu A.
Salys Casimer K.
Yoo Do Hyun
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