Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-22
2003-11-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06654942
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design of microprocessors. In particular, the present invention relates to method and system for providing compact, netlist driven top level routing approach for microprocessor family designs.
2. Description of the Related Art
To maintain a competitive edge in the market for microprocessors, it is imperative to reduce the time needed to realize the microprocessor design into a viable commercial product while at the same time increasing the speed and reliability of the microprocessor. To this end, in designing each successive generation of microprocessors within a given family of microprocessor design (for example, Sun SPARC microprocessors from Sun Microsystems, Inc., or x486 family for microprocessors from Intel Corporation), it is important to extract as much of the existing design as possible from the existing family of microprocessors in the design and implementation of the successive microprocessor.
Existing processor design techniques help only to a certain extent in extending the life of a particular family of microprocessors. Indeed, in most cases, many of the design issues have been considered and incorporated in the early stages of the particular microprocessor family development. To increase the speed as well as reliability, while holding onto a majority of the old design, new and robust CAD techniques and initiatives are necessary. This is particularly acute in the case of designing microprocessors with greater than 20 million transistor count.
Presently available design approaches to maintain or extract many of the existing features of a microprocessor family while improving the speed and reliability of each successive microprocessor in a given family include, for example, adding a second level on a chip cache, moving to a smaller transistor width process technology, and taking advantage of advanced tools to route the chip more effectively.
While the approaches discussed above may be applied to a particular design of microprocessors, it remains important to maintain the design of prior generation of microprocessors in the design of each successive microprocessor. That is, the CAD tools that were used in the design process should preferably be continued with the design of each successive generation of microprocessors. Indeed, it would be desirable to have new CAD techniques that would permit taking advantage of the new design tools while preserving the use of the old design tools.
SUMMARY OF THE INVENTION
In view of the foregoing, a method of providing a netlist driven routing in accordance with one embodiment of the present invention may include the steps of retrieving one or more design parameters and one or more top level design criteria, translating said retrieved one or more design parameters and said top level design criteria, generating one or more top level re-routes based on said translated one or more design parameters and top level design criteria, and converting said generated one or more top level re-routes into a compatible syntax.
The one or more design parameters may include a die size, a metal orientation information of the routing layer, and a timing information. Furthermore, the one or more top level design criteria may include connectivity information corresponding to a plurality of block components of an existing design layout. Additionally, the one or more top level design criteria may include a plurality of abstracts of block components, while the one or more of design parameters may include one or more netlists.
In a further aspect of the present invention, each of said one or more netlists may include a connectivity information corresponding to a respective one or more of block components.
Moreover, said connectivity information of said respective one or more of said block components may include a pin name information of each of said block components and a connection information corresponding to each of said pin name information.
Additionally, the generating step may include the step of optimizing each of said one or more top level re-routes.
Further, the method in one aspect of the present invention may include the step of verifying said compatible syntax, where the verifying step may include the step of comparing said converted one or more top level re-routes with a corresponding one or more netlists.
Moreover, the corresponding one or more netlists may include connection information related to an existing design layout of a microprocessor.
A method of providing a netlist driven routing in accordance with another embodiment of the present invention includes the steps of retrieving one or more design parameters and one or more top level design criteria, translating said retrieved one or more design parameters and said top level design criteria, generating one or more top level re-routes based on said translated one or more design parameters and top level design criteria, converting said generated one or more top level re-routes into a compatible syntax, and verifying said compatible syntax.
An apparatus for providing a netlist driven routing in accordance with yet another embodiment of the present invention includes means for retrieving one or more design parameters and one or more top level design criteria, means for translating said retrieved one or more design parameters and said top level design criteria, means for generating one or more top level re-routes based on said translated one or more design parameters and top level design criteria, and means for converting said generated one or more top level re-routes into a compatible syntax.
The one or more design parameters may include a die size, a metal orientation information of the routing layer, and a timing information.
The one or more top level design criteria may include connectivity information corresponding to a plurality of block components of an existing design layout.
Furthermore, the one or more top level design criteria may include a plurality of abstracts of block components, while the one or more of design parameters may include one or more netlists.
Additionally, each of said one or more netlists may include a connectivity information corresponding to a respective one or more of block components, where the connectivity information of said respective one or more of said block components may include a pin name information of each of said block components and a connection information corresponding to each of said pin name information.
Furthermore, the generating means may include means for optimizing each of said one or more top level re-routes, while the apparatus may additionally include means for verifying said compatible syntax.
Moreover, the verifying means may include means for comparing said converted one or more top level re-routes with a corresponding one or more netlists, where the corresponding one or more netlists may include connection information related to an existing design layout of a microprocessor.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
REFERENCES:
patent: 5483461 (1996-01-01), Lee et al.
patent: 5586319 (1996-12-01), Bell
patent: 5901064 (1999-05-01), Weber et al.
patent: 5995730 (1999-11-01), Blinne
patent: 6077308 (2000-06-01), Carter et al.
patent: 6230301 (2001-05-01), Weber
Chen Hsiu-Nien
Chopra Sachin
Fu Peter
Kim Von-Kyoung
Lai Peter
Martine & Penilla LLP
Siek Vuthe
Sun Microsystems Inc.
Tat Binh
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