Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-05-23
2006-05-23
Ellis, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S127000, C711S005000, C345S540000, C365S233100, C370S509000, C714S752000, C714S702000, C714S727000
Reexamination Certificate
active
07051171
ABSTRACT:
A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.
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Ayers Thomas
Liu Binfan
Wang Zhongqiang
BroadLogic Network Technologies Inc.
Chery Mardochee
Ellis Kevin
Townsend and Townsend / and Crew LLP
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