Method and system for protecting a stacked gate edge in a semico

Details Method and system for protecting a stacked gate edge in a semico Method and system for protecting a stacked gate edge in a semico

1996-12-18

1997-12-02

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257346, H01L 29788, H01L 2976, H01L 2994, H01L 31062

Patent

active

056939728

ABSTRACT:
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

REFERENCES:
patent: 4810666 (1989-03-01), Taji
patent: 5297082 (1994-03-01), Lee

Affiliated with

Also associated with

Rating

Method and system for protecting a stacked gate edge in a semico does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for protecting a stacked gate edge in a semico, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for protecting a stacked gate edge in a semico will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-804172