Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-13
2010-10-26
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07823110
ABSTRACT:
A method and system for processing geometrical layout design data in a computation network. The method includes assigning one or more partitions of the geometrical layout design data to one or more computing devices. One or more partitions are assigned based on first predefined parameters. The method further includes receiving a minimum-hierarchy representation of the geometrical layout design data and a partition information corresponding to one or more partition assigned. The partition information corresponding to a partition assigned includes a spatial information corresponding to the partition. Further, the minimum-hierarchy representation includes a plurality of cells. Each cell in the minimum-hierarchy representation may include zero or more bounding box information and zero or more cell-references. Further, the method includes retrieving one or more fragments based on each of the partition information and the minimum-hierarchy representation. A fragment can include one or more parts of a cell of the geometrical layout design data.
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Bhat Nitin P
Pai Ravi R.
Pereira Mark
Global IP Services PLLC
Kik Phallaka
Nama Prakash
SoftJin Technologies Private Limited
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