Method and system for processing a multiple-register instruction

Details Method and system for processing a multiple-register instruction Method and system for processing a multiple-register instruction

1996-12-16

1999-06-15

Lim, Krisna

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395566, 395567, 395595, 39580023, 711200, 711201, G06F 900, G06F 930

Patent

active

059130547

ABSTRACT:
A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

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