Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-04-29
1998-07-28
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518507, G06F 1216
Patent
active
057874794
ABSTRACT:
A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.
REFERENCES:
patent: 5091850 (1992-02-01), Culley
patent: 5124568 (1992-06-01), Chen et al.
Jessani Romesh Mangho
Kuttanna Belliappa Manavattira
Mallick Soummya
Patel Rajesh Bhikhubhai
Chan Eddie P.
Dillon Andrew J.
International Business Machines - Corporation
Motorola Inc.
Ng Antony P.
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