Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-04
2005-01-04
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06839887
ABSTRACT:
One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.
REFERENCES:
patent: 5666288 (1997-09-01), Jones et al.
patent: 6381563 (2002-04-01), O'Riordan et al.
J.D. Conway et al., “An Automatic Layout Generator for Analog Circuits,” 1992 IEEE, pp. 513-519.*
M. Dessouky et al., “Layout-Oriented Synthesis of High Performance Analog Circuits,” ACM 2000, pp. 53-57.*
J.A. Prieto et al., “A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's,” 1997 IEEE, pp. 389-394.*
Ferrario et al., “Moving from Mixed Signal to RF Test Hardware Development,” 2001 ITC Int'l Test Conference, Paper 34.1, pp. 948-956.*
Miliozzi et al., “A Design System for RFIC: Challenges and Solutions,” Proceedings of the IEEE, vol. 88, No. 10, Oct. 2000, pp. 1613-1632.*
Charbon et al., “Generalized Constraint Generation for Analog Circuit Design,” 1993 IEEE/ACM Int'l Conference on CAD, pp. 408-414.
Bhattacharyya Bijan
Brotman Andy
Lampaer Koen
Matloubian Mishel
Miliozzi Paolo
Conexant Systems Inc.
Farjami & Farjami LLP
Garbowski Leigh M.
LandOfFree
Method and system for predictive multi-component circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for predictive multi-component circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for predictive multi-component circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3380860