Method and system for predicting the performance benefits of...

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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C711S202000, C711S203000, C711S206000, C703S013000, C703S014000, C703S021000, C703S022000

Reexamination Certificate

active

07376808

ABSTRACT:
A method for modeling the performance of memory address translation mechanism (MATM), comprises: a) receiving an execution profile that contains a memory address reference stream of an application, a set of page size mappings, and events about the application's data allocations and de-allocations; b) translating each memory reference in the input memory reference stream into a reference to the corresponding data object, by consulting the memory allocation and de-allocation events, to provide a data object reference stream; c) translating each data object reference into a corresponding page reference by consulting the page size mapping and by modeling the data allocation and de-allocation events in accordance with the mapping to provide a page reference stream and a number of pages of each page size that are needed by the respective mapping; d) using the page reference stream to provide a stream of reuse distance values; e) determining, for each reference in the reuse distance value stream, whether the reference results in a hit or a miss reference to the MATM to provide the number of hits and the number of misses for each MATM; f) providing the hit and miss values to a cost model to estimate the number of miss cycles; g) ranking the mappings by their miss cycle values such that the mapping with the lowest number of miss cycles has the highest rank.

REFERENCES:
patent: 5937437 (1999-08-01), Roth et al.
patent: 6751583 (2004-06-01), Clarke et al.
patent: 2005/0268039 (2005-12-01), Archambault et al.

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