Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-07
2005-06-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06904584
ABSTRACT:
A method and system for placing logic nodes based on an estimated wiring congestion are provided. Specifically, under the present invention, relative probabilities for potential implementations of wiring interconnects between logic nodes are determined. Then, for each edge between adjacent bins, a total of corresponding relative probabilities is compared to a wiring availability. Based on the comparison, the logic nodes can be placed within wiring constraints.
REFERENCES:
patent: 4890238 (1989-12-01), Klein et al.
patent: 5124273 (1992-06-01), Minami
patent: 5640327 (1997-06-01), Ting
patent: 5856927 (1999-01-01), Greidinger et al.
patent: 5930499 (1999-07-01), Chen et al.
patent: 6110222 (2000-08-01), Minami et al.
patent: 6192508 (2001-02-01), Malik et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6314547 (2001-11-01), Donath et al.
patent: 6367051 (2002-04-01), Pileggi et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6651232 (2003-11-01), Pileggi et al.
patent: 6778999 (2004-08-01), Hathaway
patent: 6792582 (2004-09-01), Cohn et al.
patent: 2001/0003843 (2001-06-01), Scepanovic et al.
patent: 2001/0009031 (2001-07-01), Nitta et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2001/0014965 (2001-08-01), Hiraga
patent: 2002/0087940 (2002-07-01), Greidinger et al.
patent: 2002/0170020 (2002-11-01), Darden et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2003/0182649 (2003-09-01), Harn
Yang et al., “Congestion Reduction During Placement Based on Integer Programming”, IEEE/ACM International Conference on Computer Aided Design, Nov. 4, 2001, pp. 573-576.
Eisenmann et al., “Generic Global Placement and Floorplanning”, Proceedings of Design Automation Conference, Jun. 15, 1998, pp. 269-274.
Schulz, “Hierarchical Physical Design System”, Proceedings of VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks, May 8, 1989, pp. 5/20-5/24.
Fernandez et al., “Efficient VLSI Layouts for Homogeneous Product Networks”, IEEE Transcations on Computers, vol. 46, No. 10, Oct. 1997, pp. 1070-1082.
Hou et al., “A New Congestion-Driven Placement Algorithm based on Cell Inflation”, Proceedings of the 2001 Asia and South Pacific Design Automation Conference, Jan. 30, 2001, pp. 605-608.
Sadakane et al., “A Congestion-Driven Placement Improvement Algorithm for Large Scale Sea-of-Gate Arrays”, Proceedings o the IEEE 1997 Custom Integrated Circuits Conference, May 5, 1997, pp. 573-576.
NB8909290, “Method to Improve Chip Wiring”, IBM Technical Disclosure Bulletin, vol. 32, No. 4B, Sep. 1989, pp. 290-293 (6 pages).
NN83102625, “Estimating Chip Wirability by Routing Configuration Averaging”, IBM Technical Disclosure Bulletin, vol. 26, No. 5, Oct. 1983, pp. 2625-2633 (12 pages).
NN7308734, “Prewire Prediction Model”, IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 734-744 (15 pages).
NNRD454151, “Congestion Driven Placement System Using Mid-Cut Partitioning”, IBM Technical Disclosure Bulletin, No. 454, Feb. 1, 2002, p. 318(6 pages).
NB9406185, “Statistical Mehtod of Noise Estimation in a Synchronous System”, IBM Technical Disclosure Bulletin, vol. 37, No. 6B, Jun. 1994, pp. 185-194 (16 pages).
NN920822, “Global Routing Techniques for Signal Crosstalk Avoidance and Prediction”, IBM Technical Disclosure Bulletin, Vo 35, No. 3, Aug. 1992, pp. 22-28 (11 pages).
NA920371, “Technique to Allocate Space on VLSI Chips for Design Changes”, IBM Technical Disclosure Bulletin, vol. 34, No. 10A, Mar. 1992, pp. 71-72 (4 pages).
NN74033422, “Premaze Runner Analyzer”, IBM Technical Disclosure Bulletin, vol. 16, No. 10, Mar. 1976, pp. 3422-3425 (6 pages).
Brenner Ulrich
Honsinger Philip S.
Koehl Juergen
Korte Bernhard
Rohe Andre
Hoffman Warnick & D'Alessandro LLC
Kik Phallaka
Kotulak Richard M.
LandOfFree
Method and system for placing logic nodes based on an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for placing logic nodes based on an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for placing logic nodes based on an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3479365