Method and system for performing static timing analysis on...

Details Method and system for performing static timing analysis on... Method and system for performing static timing analysis on...

2007-03-20

2007-03-20

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10709376

ABSTRACT:
A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file is converted to a group of cutpoints, and formal verification is performed on the cutpoints. A determination is made as to whether or not the cutpoints pass formal verification. If the cutpoints pass formal verification, the user analysis on the final circuit netlist is completed, and the final circuit netlist can proceed to manufacturing. Otherwise, if the cutpoints do not pass formal verification, a flag is issued to alert a user. The user then has to either modify certain snip point(s) within the snip file or modify the circuit netlist, and perform the user analysis again.

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