Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-12-19
2004-05-11
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000
Reexamination Certificate
active
06735140
ABSTRACT:
TECHNICAL FIELD
Embodiments of the present invention relate generally to memory systems. In particular, an embodiment of the present invention relates to a method for performing memory operations of a memory device.
BACKGROUND ART
Some memory systems require periodic refreshing to maintain the voltage levels that are stored in their memory cells. A refresh operation may be a word line activation that restores the voltage level of the data stored in a memory cell. Some high density SRAMs (e.g., static random access memory) are characterized by memory cell structures that require DRAM (dynamic random access memory) type refreshes even though standard SRAM timing interfaces are employed in their construction. This requirement necessitates the hiding of these DRAM type operations (e.g., making them transparent to a user) within standard SRAM timing configurations.
Many conventional methodologies for hiding DRAM type operations within standard SRAM timing configurations employ pulsed read and write cycles and feature the inhibition of refresh operations during the active portions of these cycles. Many applications of such methodologies are characterized by the toggling of memory addresses. These applications feature the activation of word lines whenever such memory addresses are toggled. A drawback of such methodologies is that when sub-minimum cycles are encountered, and the addresses are toggled very closely together, a continuous activating and deactivating of word lines at maximum frequencies may result. Consequently, because refresh operations may be inhibited during the activation of a word line (e.g., the active cycle), it may be difficult for a refresh operation to be executed in cases where such sub-minimum cycles are encountered.
Another drawback of conventional methodologies is the cycle time limitations that result from the need to accommodate the occurrence of late write operations. It should be appreciated that the pulsed word line activations that are employed in the execution of periodic refresh operations may expose such cycle time limitations. For example, if a refresh timer expires during the time interval between the initiation of read and write enable commands, a pulsed refresh operation may be executed before the execution of the enabled write operation. Consequently, it may be necessary to accommodate three memory cycles (e.g., read, refresh and write) within a single cycle time window of the overall system cycle. As a result, the speed of the memory device may be degraded by the constraint on cycle time imposed by the need to accommodate the three operations.
FIG. 1
is a state diagram
100
with states
1
-
4
which illustrate a process for hiding refresh operations according to a conventional scheme.
FIG. 1
shows blocks representing logic states
1
-
4
that correspond to precharge
101
, refresh
104
, read
102
(new address), write (new address)
103
, and standby
106
operations. Also shown in
FIG. 1
is refresh timer
105
and a block
105
a
representing the posting of the refresh operation (e.g., refresh posted
105
a
).
Referring to
FIG. 1
, when either a read or a write command is received and the memory device corresponding to state diagram
100
is in precharge state
1
(e.g.,
101
), the memory device may perform a read operation
102
or a write operation
103
(depending on the command received) and then return to precharge state
1
where precharge operations
101
may be resumed. However, as is shown in
FIG. 1
, if the refresh timer
105
expires the memory device may perform a refresh operation
104
(e.g., state
4
) and thereafter return to precharge state
1
(e.g.,
101
).
FIG. 2
shows a timing diagram
200
that illustrates characteristics of the various read and write operations (e.g.,
102
and
103
) employed by the memory device (not shown) corresponding to state diagram
100
of FIG.
1
. It should be appreciated that many conventional systems continually inhibit refresh operations during the active cycles (e.g., during the performance) of read
102
and write
103
operations, which may prevent the execution of and the posting (e.g.,
105
a
) of refresh operations
104
.
FIG. 2
shows read operation timing diagram
120
, write operation timing diagram
121
and standby mode timing diagram
122
.
Referring to
FIG. 2
, read operation timing diagram
120
and write operation timing diagram
121
show that when either a read or a write command is received and the memory device is in precharge state
1
(e.g.,
101
), the memory device may perform a read operation
102
(e.g., state
2
) or a write operation
103
(e.g., state
3
) (either to a new address or to the same address) and may then return to precharge state
1
where precharge operations
101
may be resumed. Standby timing diagram
122
shows that these operations may be performed when the device has exited the standby mode
106
(e.g., low power mode). The timing diagrams depicted represent a typical functioning of read
102
and write
103
operations in a conventional memory device.
FIG. 3
shows a timing diagram that illustrates characteristics of the refresh operations (e.g.,
104
) employed by a memory device corresponding to state diagram
100
of FIG.
1
.
FIG. 3
shows precharge operation timing diagram
131
, read operation timing diagram
120
a
, write operation timing diagram
121
a
, standby mode timing diagram
122
a
, refresh operation timing diagram
133
and refresh timer diagram
134
.
Referring to
FIG. 3
, timing diagrams
300
show that when the refresh timer
105
expires during a read operation
102
, the refresh operation
104
may be inhibited until the read operation
102
is completed as is shown by timing diagrams
120
a
,
133
and
134
(e.g., corresponding respectively to the read
102
, refresh
104
and refresh timer
105
operations). Upon the termination of the read operation, if another command has not yet occurred, an ensuing refresh operation
104
may be performed as is again shown by timing diagrams
120
a
,
133
and
134
. It should be appreciated that precharge timing diagram
131
, write operation timing diagram
121
a
, and standby mode timing diagram
122
a
(e.g., corresponding respectively to precharge
101
, write
103
, and standby
106
operations) illustrate the functioning of their corresponding memory operations in the context of the conventional refresh hiding scheme employed by a memory device corresponding to state diagram
100
of FIG.
1
.
FIG. 4
shows a timing diagram that illustrates the sub minimum cycle response of a conventional memory device such as described above with reference to
FIGS. 1-3
. Because the conventional refresh hiding methodologies described by
FIGS. 1-3
may block refresh operations
104
during read and write cycles (e.g., during read operations and write operations
102
and
103
), a refresh operation
104
may be inhibited (e.g., as by inhibit refresh
405
) during this entire period if a memory device is operated at sub-minimum access (e.g., one example is address toggling
403
) as is illustrated in FIG.
4
. It should be appreciated that when addresses are toggled very closely together such as is shown in
FIG. 4
(see timing diagram
403
), the continuous activating and closing of word lines at maximum frequencies may result. As is shown in
FIG. 4
, this may correspond to memory device behavior such as the execution of successive read operations
102
(e.g.,
407
) in a manner that blocks the enablement of refresh operations thereby making it difficult for a refresh operation
104
to be executed. All of the aforementioned memory operations may be enabled during the cycle time window
401
a
shown in chip enable timing diagram
401
.
FIG. 5
shows a timing diagram that illustrates cycle time constraints (e.g., limitations) that in the case of late writes require a read, refresh, and write operations to occur within a single cycle time window of an overall system cycle. It should be appreciated that as suggested the cycle time of a memory device may be limited in some
Chapman Dave
Fiscus Tim
Cypress Semiconductor Corporation
Wagner , Murabito & Hao LLP
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