Static information storage and retrieval – Systems using particular element – Magnetic thin film
Reexamination Certificate
2003-06-10
2004-11-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetic thin film
C365S203000, C365S210130
Reexamination Certificate
active
06826079
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to random access memory for data storage. More specifically, the present invention relates to a magnetic random access memory device that includes an array of memory cells and differential sense amplifiers working in conjunction with unidirectional elements to limit leakage current within the array.
Magnetic random access memory (“MRAM”) is a non-volatile memory that shows considerable promise for long-term data storage. Performing read and write operations on MRAM devices are much faster than performing read and write operations on conventional memory devices such as DRAM and Flash and order of magnitude faster than long-term storage devices such as hard drives. In addition, the MRAM devices are more compact and consume less power than other conventional storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend across rows of the memory cells and bit lines extend along columns of the memory cells. Each memory cell is located at a crosspoint of the word line and a bit line.
A memory cell stores a bit of information as an orientation of a magnetization. The magnetization of each memory cells assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “0” and “1”.
The magnetization orientation affects the resistance of a memory cell such as a spin-tunneling device. For instance, resistance of a memory cell is a first value R if the magnetization orientation is parallel and resistance of the memory cell is increased to a second value R+&Dgr;R if the magnetization orientation is changed from parallel to anti-parallel. The magnetization orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance state of the memory cell. The memory cells thus form a memory array of resistive crosspoints.
Applying a voltage to a selected memory cell and measuring a sense current that flows through the memory cell may sense the resistance state. The resistance would be determined by the ratio of applied voltage and the sense current (R=V/I).
Sensing the resistance state of a single memory cell in an array, however, can be unreliable. All memory cells in the array are coupled together through many parallel paths. The resistance seen at one crosspoint equals the resistance of the memory cell at that crosspoint in parallel with resistances of memory cells in the other rows and columns of the array.
Moreover, if the memory cell being sensed has a different resistance due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to a parasitic or “sneak path” current, which is also known as a leakage current. The parasitic or leakage current becomes large in a large array and, therefore, can obscure the sense current. Consequently, the parasitic current can prevent the resistance from being sensed.
Unreliability in sensing the resistance state is compounded by manufacturing variations, variations in operating temperatures of the MRAM devices. These factors can cause the average value of resistance in the memory cell to vary.
The prior art has attempted to reduce, if not actually eliminate leakage current through various designs. One approach involves adding a unidirectional element, such as a diode, to limit the current path in one direction.
FIG. 1
illustrates such an embodiment. The memory cell
4
includes a diode
6
to limit current flow in the direction dictated by the diode
6
. When a sense current is applied as shown in
FIG. 1
, the current actually measured by the sense amplifier is the sense current I_s flowing through the intended cell
4
, and the leakage current I_leak, which flows through several other memory cell/diode pairs. This additional leakage current reduces the operating range of the sense amplifier. Further, as the size of the memory array increases, the leakage current dominates the sense signal, reducing even more the operating range of the sense amplifier. Additionally, noise increases in the sensing amplifier because of the leakage current paths.
Accordingly, there is a need to be able to sense the resistance states of the memory cells within the MRAM devices in a reliable fashion. Further, there is a need to limit the parasitic or leakage current that exists between cells not being sensed within the array during a read operation.
SUMMARY OF THE INVENTION
According to the present invention, a method and system for minimizing a leaked current within an array of memory cells as well as a method and system for differentiating a resistive value within a sensed memory cell during a read operation are disclosed. The memory array includes a plurality of bit lines and word lines that are cross-coupled via a plurality of memory cells. Each memory cell is limited in providing a conductive path in a first direction only by way of a unidirectional element. Such unidirectional elements typically comprise of diodes. The apparatus utilizes the diodes to form a current path from the word line to the bit line having passed through the diode and resistive memory cell. Further, a differential sense amplifier is utilized to differentiate the sensed current during a read operation from a reference value after an equipotential value is placed across the array to limit leakage current from developing within adjoining word and bit lines during a sense operation of a given memory cell.
REFERENCES:
patent: 5347485 (1994-09-01), Taguchi et al.
patent: 5911193 (1999-06-01), Johnson
patent: 6011739 (2000-01-01), Baek
patent: 6130538 (2000-10-01), Carrozzi et al.
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