Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-30
2009-06-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07549134
ABSTRACT:
Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.
REFERENCES:
patent: 6018623 (2000-01-01), Chang et al.
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6539527 (2003-03-01), Naffziger et al.
patent: 6772403 (2004-08-01), Sasaki
patent: 6832180 (2004-12-01), Sutera et al.
Khan et al. “A 150-MHz Graphics Rendering Processor With 256-Mb Embedded DRAM,” IEEE Journal of Solid State Circuits, Nov. 2001, vol. 36, No. 11, pp. 1775-1784.
Niemazie et al. “260Mb/s Mixed-Signal Single-Chip Integrated System Electronics fro Magnetic Hard Disk Drive,” 1999 IEEE International Solid-State Circuits Conference / Session 2 / Paper MP 2.5, Feb. 1999, Digest of Technical Papers, pp. 42-43 and 443.
Khan et al. “A 150MHz Graphics Rendering Processor with 255-Mb Embedded DRAM,” ISSCC 2001 / Section 9 / Integrated Multimedia Processors / 9.6, Feb. 2001, pp. 150-151 and 442.
Sani Nassil, “Delay Variability: Sources, Impact and Trends,” ISSCC 2000 / Session 22 / TD: Low-Power and Digital Techniques / Paper VP 22.4, Feb. 2000, pp. 368-369, Digest of Technical Papers.
McCormick et al. “Waveform Moment Methods for Improved Inteconnection Analysis,” 27th ACM/IEEE Design Automation Conference, 19990, pp. 406-412.
Ratzlaff et al. “RICE: Rapid Interconnect Circuit Evaluator,” 28th ACM/IEEE Design Automation Conference, Paper 33.1, 1991, pp. 555-560.
Pillage, et al. “Asymptotic Waveform Evaluation for Timing Analysis,” IEEE Transactions on Computer Aided Design, Apr. 1990, vol. 9 No. 4, pp. 352-366.
S. Naffziger, “Design Methodologies for Interconnects in GHZ+ ICs,” IEEE International Solid State Circuits Conference Short Course, Feb. 1999.
Khan, “Physical Design Methodology Best Practices: Nanometer and RTL-down closure,” IEEE DATC Electronic Design Processes Workshop, Monterey, California, Apr. 2001.
Chiu Hsien-Yen
Li Jun
Spyrou Athanasius
Zhao Hong
Bowers Brandon W
Cadence Design Systems Inc.
Chiang Jack
Vista IP Law Group LLP
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