Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-17
2002-07-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C327S010000
Reexamination Certificate
active
06415422
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to data processing in general and, in particular, to a method and system for performing capacitance estimations on an integrated circuit design. Still more particularly, the present invention relates to a method and system for performing capacitance estimations on an integrated circuit design that is routed utilizing a global routing tool.
2. Description of the Prior Art
A microelectronic integrated circuit (IC) typically comprises a large number of electronic components that are fabricated by layering several different materials on a silicon wafer. Signals are communicated among these electronic components via interconnects. Thus, path delays in an IC are typically dominated by the signal propagation time of interconnects within the IC. In order to properly estimate the signal propagation time of interconnects within an IC during its design, it is crucial to determine the electrical characteristics (including distributed capacitance and resistance) of the interconnects within the IC design. However, the routing of interconnects is typically not completed until the end of the IC design process.
Instead of waiting until the completion of interconnect routing, capacitance estimations for interconnects are conventionally accomplished by constructing a Steiner tree route for a net (ignoring congestion and blockages) and by computing capacitance based on the Steiner tree route. However, there are two primary drawbacks to the conventional method of capacitance estimation. First, the Steiner tree topology is highly inaccurate, and second, a worst-case capacitance computation is typically obtained. As a result, the conventional method of capacitance estimation leads to a more conservative IC design than it is necessary. Consequently, it would be desirable to provide a better method to perform capacitance estimations on an IC design before the detailed routing of interconnects is completed.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, routing areas and pin locations of a net within an integrated circuit design are obtained from a global routing tool. Common boundaries among the routing areas are then defined. Before the performance of a detailed routing step, congestion information furnished by the global routing tool is utilized to perform probabilistic capacitance calculations for an interconnect that can be routed within the routing areas via the defined common boundaries to connect the pin locations.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 2001/0047507 (2001-11-01), Pileggi et al.
Kay, et al., “PRIMO:Probability Interpretation of Moments for Delay Calculation”; Design Automation Conference; pp. 469-472; 1998.*
Togawa, et al., “Maple-opt: A Performance-Oriented Simultaneous Technology Mapping Placement, and Global Routing Algorithm for FPGA's”; IEEE Trans. on CAD of ICs and Systems; 1998.
Mehrotra Sharad
Patel Parsotam Trikam
Bracewell & Patterson L.L.P.
Dinh Paul
International Business Machines - Corporation
Salys Casimer K.
Smith Matthew
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