Method and system for partitioning integrated circuits

Details Method and system for partitioning integrated circuits Method and system for partitioning integrated circuits

2006-03-27

2010-11-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S014000

Reexamination Certificate

active

07836419

ABSTRACT:
Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.

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