Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-12
2010-02-02
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000
Reexamination Certificate
active
07657856
ABSTRACT:
Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
REFERENCES:
patent: 5581475 (1996-12-01), Majors
patent: 5828880 (1998-10-01), Hanko
patent: 5870313 (1999-02-01), Boyle et al.
patent: 6003066 (1999-12-01), Ryan et al.
patent: 6009250 (1999-12-01), Ho et al.
patent: 6035107 (2000-03-01), Kuehlmann et al.
patent: 6047116 (2000-04-01), Murakami et al.
patent: 6066179 (2000-05-01), Allan
patent: 6185583 (2001-02-01), Blando
patent: 6237128 (2001-05-01), Folberth et al.
patent: 6289369 (2001-09-01), Sundaresan
patent: 6324673 (2001-11-01), Luo et al.
patent: 6389451 (2002-05-01), Hart
patent: 6505327 (2003-01-01), Lin
patent: 6519749 (2003-02-01), Chao et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: 6560766 (2003-05-01), Pierrat et al.
patent: 6574788 (2003-06-01), Levine et al.
patent: 6629293 (2003-09-01), Chang et al.
patent: 6701504 (2004-03-01), Chang et al.
patent: 6721928 (2004-04-01), Pierrat et al.
patent: 6738954 (2004-05-01), Allen et al.
patent: 6829757 (2004-12-01), Teig et al.
patent: 6996790 (2006-02-01), Chang
patent: 7047506 (2006-05-01), Neves et al.
patent: 7051307 (2006-05-01), Ditlow et al.
patent: 7089511 (2006-08-01), Allen et al.
patent: 7107559 (2006-09-01), Lakshmanan et al.
patent: 7155698 (2006-12-01), Gennari
patent: 7177859 (2007-02-01), Pather et al.
patent: 7266795 (2007-09-01), Baumgartner et al.
patent: 7318214 (2008-01-01), Prasad et al.
patent: 7340742 (2008-03-01), Tabuchi
patent: 7401208 (2008-07-01), Kalla et al.
patent: 7421505 (2008-09-01), Berg
patent: 7500217 (2009-03-01), Cote et al.
patent: 2001/0003843 (2001-06-01), Scepanovic et al.
patent: 2002/0049956 (2002-04-01), Bozkus et al.
patent: 2003/0012147 (2003-01-01), Buckman et al.
patent: 2003/0023939 (2003-01-01), Pierrat et al.
patent: 2003/0037117 (2003-02-01), Tabuchi
patent: 2004/0015256 (2004-01-01), Conrad et al.
patent: 2004/0019679 (2004-01-01), E et al.
patent: 2004/0019892 (2004-01-01), E et al.
patent: 2004/0044979 (2004-03-01), Aji et al.
patent: 2004/0098511 (2004-05-01), Lin et al.
patent: 2004/0199887 (2004-10-01), Jain et al.
patent: 2004/0268354 (2004-12-01), Kanai et al.
patent: 2005/0038852 (2005-02-01), Howard
patent: 2005/0091634 (2005-04-01), Gallatin et al.
patent: 2005/0097561 (2005-05-01), Schumacher et al.
patent: 2005/0102681 (2005-05-01), Richardson
patent: 2005/0132320 (2005-06-01), Allen et al.
patent: 2005/0138474 (2005-06-01), Jain et al.
patent: 2005/0166173 (2005-07-01), Cote et al.
patent: 2005/0216870 (2005-09-01), DeCamp et al.
patent: 2005/0216875 (2005-09-01), Zhang et al.
patent: 2005/0262510 (2005-11-01), Parameswaran et al.
patent: 2006/0062430 (2006-03-01), Vallone et al.
patent: 2006/0123420 (2006-06-01), Nishikawa
patent: 2006/0230370 (2006-10-01), Baumgartner et al.
patent: 2006/0265675 (2006-11-01), Wang
patent: 2007/0079268 (2007-04-01), Jones et al.
patent: 2007/0192545 (2007-08-01), Gara et al.
patent: 2007/0220232 (2007-09-01), Rhoades et al.
patent: 2007/0233805 (2007-10-01), Grodd et al.
patent: 2007/0271562 (2007-11-01), Schumacher et al.
patent: 2009/0125867 (2009-05-01), Cote et al.
Office Action dated Jan. 11, 2008 for U.S. Appl. No. 11/228,472.
Office Action dated Aug. 24, 2007 for U.S. Appl. No. 11/228,472.
Office Action dated Jan. 18, 2007 for U.S. Appl. No. 11/228,472.
Office Action dated Sep. 28, 2007 for U.S. Appl. No. 11/225,816.
Office Action dated Sep. 7, 2007 for U.S. Appl. No. 11/225,853.
Office Action dated Mar. 9, 2007 for U.S. Appl. No. 11/225,853.
Office Action dated Sep. 17, 2007 for U.S. Appl. No. 11/225,815.
Bender, M.A. et al. “On-the-Fly Maintenance of Series-Parallel Relationships in Fork-Join Multithreaded Programs” Proceedings of the 16th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Barcelona, Spain, 2004, pp. 133-144.
Cadence Design Systems, Inc. “Assura Layout vs. Schematic Verifier” 2003, 4 pgs., Cadence Design Systems, Inc., San Jose, CA.
Ferguson, J. “Calibre MTflex: Reducing the High Cost of Processing Power”, Mar. 2004, 5 pgs., Mentor Graphics Corporation, San Jose, CA.
Fliesler, M. “Mentor Consulting Helps AMD Win Another Race to Market”, 2001, pp. 1-5, Mentor Graphics Corporation, San Jose, CA.
Kalas, I. et al. “FTL: A Multithreaded Environment for Parallel Computation” Proceedings of the 1994 Conference of the Centre for Advanced Studies on Collaborative Research, Toronto, Ontario, Canada, 1994, pp. 1-12.
Krishnaswamy, V. et al. “Actor Based Parallel VHDL Simulation Using Time Warp” Proceedings of the 10th Workshop on Parallel and Distributed Simulation, 1996, pp. 135-142.
Lee, P.M. et al. “A Parallel and Accelerated Circuit Simulator with Precise Accuracy” Proceedings of the 15th International Conference on VLSI Design (VLSI '02), Bangalore, India, Jan. 7-11, 2002, pp. 1-6.
Magarshack, P. et al. “System-on-Chip Beyond the Nanometer Wall” Proceedings of the 40th Conference on Design Automation (DAC '03), Anaheim, CA, Jun. 2-6, 2003, pp. 419-424.
Mentor Graphics Corporation “Mentor Graphics Unveils Calibre MTflex to Combat Cost of Nanometer Design Compute Requirements”, May 12, 2003, 2 pgs., Mentor Graphics Corporation, San Jose, CA.
Mentor Graphics Corporation “Calibre LVS: Precise IC Layout Verification with the Schematic Design”, 2005, 4 pgs., Mentor Graphics Corporation, San Jose, CA.
Prabhu, A.M. “Management Issues in EDA” Proceedings of the 31st Conference on Design Automation (DAC '94), San Diego, CA, Jun. 6-10, 1994, pp. 41-47.
Saavedra-Barrera, R.H. et al. “Analysis of Multithreaded Architectures for Parallel Computing” Proceedings of the Second Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '90), Island of Crete, Greece, 1990, pp. 169-178.
Schellenberg, F. “Mask EDA Workshop” Copyright 1999-2001, 47 pgs., Mentor Graphics Corporation, San Jose, CA.
Spiller, M.D. et al. “EDA and the Network” Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design (CAD '97), San Jose, CA, 1997, pp. 470-476.
Office Action dated Jun. 11, 2008 for U.S. Appl. No. 11/225,853.
Office Action dated Apr. 8, 2008 for U.S. Appl. No. 11/225,816.
Banicescu, I. et al. “Overhead Analysis of a Dynamic Load Balancing Library for Cluster Computing” Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05), IEEE, 2005, p. 1.
Cadence Design Systems, Inc. “Diva Reference” Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 1 of 14, pp. 1-49.
Cadence Design Systems, Inc. “Diva Reference” Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 2 of 14, pp. 50-99.
Cadence Design Systems, Inc. “Diva Reference” Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 3 of 14, pp. 100-149.
Cadence Design Systems, Inc. “Diva Reference” Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 4 of 14, pp. 150-199.
Cadence Design Systems, Inc. “Diva Reference” Product Version 4.4.6, Jun. 2000, Cadence Design Systems, Inc. San Jose CA., part 5 of 14, pp. 200-249.
Cadenc
Cadouri Eitan
Cao Min
Koshy Mathew
Ma Li-Ling
Ruehl Roland
Cadence Design Systems Inc.
Kik Phallaka
Vista IP Law Group LLP
LandOfFree
Method and system for parallel processing of IC design layouts does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for parallel processing of IC design layouts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for parallel processing of IC design layouts will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4209950