Method and system for optimizing write combining performance in

Details Method and system for optimizing write combining performance in Method and system for optimizing write combining performance in

1998-03-31

2000-09-19

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711156, G06F 506

Patent

active

061227153

ABSTRACT:
An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.

REFERENCES:
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5630075 (1997-05-01), Joshi et al.
The UltraSPARC Processor--Technology White Paper, The UltrSPARC Architecture, Sun Microsystems, Jul. 17, 1997, p. 1.10.
21164 Alpha Microprocessor Data Sheet, Samsung Electronics, 1997.
Visual Instruction Set (VIS.TM.) User's Guide, Sun Microsystems, Version 1.1, Mar. 1997.
AMD-3D Technology Manual, AMD, Publication No. 21928, Issued Date: Feb. 1998.

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