Method and system for optimizing translation lookaside...

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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C711S205000

Reexamination Certificate

active

11083691

ABSTRACT:
A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.

REFERENCES:
patent: 6112285 (2000-08-01), Ganapathy et al.
patent: 2004/0117594 (2004-06-01), VanderSpek
patent: 2004/0215918 (2004-10-01), Jacobs et al.
Lee et al. “A dynamic TLB management structure to support different page sizes” Aug. 2000, Proceedings of the Second IEEE Asia Pacific Conference, pp. 299-302.
Romer et al. “Reducing TLB and memory Overhead Using Online Superpage Promotion” May 1995, ACM Sigarch Compute Architecture News, pp. 176-187.

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