Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
1999-03-29
2001-07-24
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S001000, C710S033000, C709S241000, C712S300000
Reexamination Certificate
active
06266723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved data processing system and, in particular, to a method and system for optimizing the transfer of data on a bus in a data processing system.
2. Description of Related Art
In conventional personal computer (PC) architectures, the CPU, main memory, and other peripheral input/output (I/O) devices are commonly coupled by a bus network having a local bus and a system bus. The system bus connects to the local bus and is generally slower than the local bus. Examples of common system bus architectures are the industry standard architecture (ISA), extended industry standard architecture (EISA) and the MicroChannel bus. The dual bus network evolved in part because early PCs required high-speed data transfer only between the CPU and the main memory. Consequently, the CPU and the main memory are situated in the faster local bus, while the video subsystem as well as other peripheral I/O devices with varying clock speeds are usually connected to the slower system bus.
Two bus architectures are currently available that allow high-speed devices to couple to the local bus to provide high data transfer rates between devices on the bus. The Video Electronics Standards Association (VESA) established a standard local bus that allowed some components, such as graphics cards, to interface directly with the local bus. In the VESA bus, the bus clock speed is controlled by the CPU clock speed. The Peripheral Component Interconnect (PCI) bus offers another architecture in which a bus controller sits between the CPU local bus and a device such as a graphics card. According to the PCI specification, a master device coupled to the PCI bus requests a data transaction with a specific target device, also coupled to the PCI bus. Both the master and target devices conduct the data transaction according to the PCI specified protocols. The PCI bus is not tied to the speed of the CPU but the PCI specification limits the bus clock speed to 33-megahertz (MHz). In either the VESA bus or the PCI bus, data transfer occurs at most only once per clock cycle, thus the bus data transfer rate is limited to the bus clock speed, thereby limiting devices that are capable of and demand higher data transfer rates.
Computer systems demand increasingly higher data transfer rates. For example, graphics oriented operating systems such as Windows and OS/2 require large amounts of data to be transferred between the central processing unit (CPU) and the devices that drive display devices such as a monitor. Even though CPU clock speeds have increased, conventional data bus architectures have created a data bottleneck between the CPU and these data intensive peripheral devices.
For some time, all PC's employed the ISA expansion bus, which was an 8-MHz, 16-bit device (actually clocked at 8.33-MHz). Using two cycles of the bus clock to complete a transfer, the theoretical maximum transfer rate was 8.33 MBytes/sec. The EISA bus was then widely used as a next generation bus. It is a 32-bit bus clocked at 8-MHz that allows burst transfers at one per clock cycle, so the theoretical maximum was increased to 33-MBytes/sec. As performance requirements increased with faster processors and memory and increased video bandwidth needs, a high-performance bus standard was a necessity. Several standards were proposed, including a MicroChannel architecture, which was a 10-MHz, 32-bit bus, allowing 40-MByte/sec, as well as an enhanced MicroChannel using a 64-bit data width and 64-bit data streaming, theoretically permitting 80-to-160 MByte/sec transfer. The requirements imposed by use of video and graphics transfer on networks, however, necessitate even faster transfer rates. One approach was the VESA (Video Electronics Standards Association) bus, which was a 33-MHz, 32-bit local bus standard specifically for an Intel 486 processor, providing a theoretical maximum transfer rate of 132-MByte/sec for burst, or 66-MByte/sec for non-burst; the 486 had limited burst transfer capability. The VESA bus was a short-term solution as higherperformance processors, e.g., the Intel P5 and P6 or Pentium and Pentium Pro processors, became the standard.
The PCI bus was proposed by Intel as a longer-term solution to the expansion bus standard, particularly to address the burst transfer issue. The original PCI bus standard has been upgraded several times, with the current standard being Revision 2.1, available from a trade association group referred to as PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214. The PCI Specification, Rev. 2.1, is incorporated herein by reference. Construction of computer systems using the PCI bus, and the PCI bus itself, are described in many publications, including “PCI System Architecture,” 3rd Ed., by Shanley et al, published by Addison-Wesley Pub. Co., also incorporated herein by reference. The PCI bus provides for 32-bit or 64-bit transfers at 33- or 66-MHz; it can be populated with adapters requiring fast access to each other and/or with system memory, and can be accessed by the host processor at speeds approaching that of the processor's native bus speed. A 64-bit, 66-MHz PCI bus has a theoretical maximum transfer rate of 528-MByte/sec. All read and write transfers over the bus can be burst transfers. The length of the burst can be negotiated between initiator and target devices and can be any length.
PCs have evolved to the point where high-speed data transfer is a critical factor in overall performance of the system. In particular, graphics intensive applications such as Computer Aided Design (CAD) require high-speed video devices that can drive high-resolution displays with more colors and three-dimensional capabilities. Video systems are being developed that require far more data transfer capability than current bus architectures and protocols can support.
Bus design and protocol is strictly regulated by industry standard specifications that dictate physical, mechanical, and electrical requirements for the bus. These specifications are necessary to ensure that devices from a wide variety of manufacturers can use the bus without negatively impacting other devices using the bus. One problem with industry standard specifications is that improvements to the bus architecture or protocol are difficult to implement. Hence, it is necessary that improvements are compatible with existing protocol and devices and comply with the industry standard specification.
Therefore, it would be advantageous to be able to implement a method for improving the speed of data transactions between a master device and a target device that is compatible with an existing bus architecture and protocol. It would be especially advantageous for the improvement to use existing, predefined bus commands in a manner that is transparent to the initiator and the target.
SUMMARY OF THE INVENTION
The present invention provides a method for optimizing bus transactions in a data processing system. A bus transaction optimizer receives an original bus transaction request which includes an original start address of a target memory for the original bus transaction, an original byte size for a number of bytes for the original bus transaction, and an original bus command for the original bus transaction. The bus transaction optimizer generates the optimal type and number of bus transaction requests required in order to complete the original bus transaction request in the shortest time frame possible irrespective of the value of the original start address or the original byte size.
The bus transaction optimizer deduces the type and number of bus transaction requests required to optimally complete the original bus transaction based upon the values of the original byte size and the original start address. The bus transaction optimizer may split the original transaction request into multiple bus transaction requests comprising both low and high performance transactions if it determines that by doing so the overall time required to complete the multiple bus transac
Abraham Leslie
Ghodrat Fataneh F.
Carstens Yee & Cahoon, L.L.P.
LSI Logic Corporation
Thai Xuan M.
LandOfFree
Method and system for optimizing of peripheral component... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for optimizing of peripheral component..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for optimizing of peripheral component... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2492016