Method and system for optimized FIFO full conduction control

Details Method and system for optimized FIFO full conduction control Method and system for optimized FIFO full conduction control

2006-07-04

2006-07-04

Nguyen, Tanh Q. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000, C710S053000, C710S055000, C710S056000

Reexamination Certificate

active

07072998

ABSTRACT:
Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

REFERENCES:
patent: 5379399 (1995-01-01), Conway-Jones et al.
patent: 5386513 (1995-01-01), Tengan
patent: 5809324 (1998-09-01), Yung
patent: 6044457 (2000-03-01), Mantor et al.
patent: 6480942 (2002-11-01), Hirairi
patent: 6658505 (2003-12-01), Jin et al.
Cache Circuitry and Operation, www.pcguide.com/ref/hdd/op/cascheCircuitry-c.html, no date.

Affiliated with

Also associated with

Rating

Method and system for optimized FIFO full conduction control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for optimized FIFO full conduction control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for optimized FIFO full conduction control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3552988