Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1994-10-05
1999-03-30
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711 3, 711108, 711133, 711202, G06F 1208
Patent
active
058902210
ABSTRACT:
An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field. The desired effective address is translated into a desired real address and a portion of the desired real address is then utilized to search each cache line for a match with the content of the second content addressable field if no match was found within the first content addressable field during the previous cycle. An offset condition is identified by comparing the translated real address to the content of the second content addressable field in a cache line when a match has occurred between the desired effective address and the content of the first content addressable field within that cache line.
REFERENCES:
patent: 3761881 (1973-09-01), Anderson et al.
patent: 4332010 (1982-05-01), Messina et al.
patent: 4400770 (1983-08-01), Chan et al.
patent: 4467411 (1984-08-01), Fry et al.
patent: 4785398 (1988-11-01), Joyce et al.
patent: 4797814 (1989-01-01), Brenza
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4890223 (1989-12-01), Cruess et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 5003459 (1991-03-01), Ramanujan et al.
patent: 5088026 (1992-02-01), Bozman et al.
patent: 5109335 (1992-04-01), Watanabe
patent: 5119290 (1992-06-01), Loo et al.
patent: 5148538 (1992-09-01), Celtruda et al.
patent: 5165028 (1992-11-01), Zulian
patent: 5230045 (1993-07-01), Sindhu
patent: 5276829 (1994-01-01), Sano
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5317738 (1994-05-01), Cochcroft, Jr. et al.
patent: 5353425 (1994-10-01), Malamy et al.
patent: 5418922 (1995-05-01), Liu
patent: 5426749 (1995-06-01), Morioka
patent: 5491806 (1996-02-01), Horstmann et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5550995 (1996-08-01), Barrera et al.
patent: 5584002 (1996-12-01), Emma et al.
patent: 5604879 (1997-02-01), Beavers et al.
patent: 5623619 (1997-04-01), Witt
patent: 5668968 (1997-09-01), Wu
Yannick Deville, A Low-cost usage-based replacement algorithm for cache memories, Computer Architecture News, pp. 52-58, No. 4, New York, Dec. 18, 1990.
G. R. Mitchell, Buffer Page Replacement, IBM Technical Disclosure Bulletin, vol. 16 No. 5, p. 1377, Oct. 1973.
Branson Brian David
Liu Peichun Peter
Chan Eddie P.
Dillon Andrew J.
International Business Machines - Corporation
Kim Hong C.
McBurney Mark E.
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