Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
1994-06-07
2001-03-27
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S023000
Reexamination Certificate
active
06209081
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application is related to U.S. patent application Ser. No. 08/001,864, entitled “Method and System for Single Cycle Dispatch of Multiple Instructions in a Superscalar Processor System”, now abandoned U.S. patent application Ser. No. 08/002,300, entitled “Method and System for Selective Serialization of Instruction Processing in a Superscalar Processor System, now abandoned U.S. patent application Ser. No. 08/001,872, entitled “Method and System for Indexing the Assignment of Intermediate Storage Buffers in a Superscalar Processor System”, now abandoned U.S. patent application Ser. No. 08/001,865, entitled “Method and System for Enhanced Instruction Dispatch in a Superscalar Processor System Utilizing Independently Accessed Intermediate Storage”, now U.S. Pat. No. 5,898,882 and U.S. patent application Ser. No. 08/001,866, entitled “Method and System for Tracking Scalar Instructions Within a Superscalar Processor System”, now abandoned all filed of even date herewith by the inventors hereof and assigned to the assignee herein.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an improved data processing system and in particular to a method and system for nonsequential instruction dispatch and execution in a superscalar processor system. Still more particularly, the present invention relates to a method and system for nonsequential instruction dispatch and execution in a superscalar processor system which permits accurate reporting of interrupts and execution.
2. Description of the Related Art
Designers of modern state-of-the-art data processing systems are continually attempting to enhance performance aspects of such systems. One technique for enhancing data processing efficiency is the achievement of short cycle times and a low Cycles-Per-Instruction (CPI) ratio. An excellent example of the application of these techniques to an enhanced data processing system is the International Business Machines Corporation RISC System/6000 (RS/6000) computer. The RS/6000 system is designed to perform well in numerically intensive engineering and scientific applications as well as in multi-user, commercial environments. The RS/6000 processor employs a superscalar implementation, which means that multiple instructions are issued and executed simultaneously.
The simultaneous issuance and execution of multiple instructions requires independent functional units that can execute concurrently with a high instruction bandwidth. The RS/6000 system achieves this by utilizing separate branch, fixed point and floating point processing units which are pipelined in nature. In view of the pipelined nature of the processors in such systems care must be taken to ensure that a result from a particular instruction which is necessary for execution of a subsequent instruction is obtained prior to dispatching the subsequent instruction. One technique for ensuring that such so-called “data dependency hazards” do not occur is the restriction of the dispatching of a particular instruction until such time as all preceding instructions have been dispatched. While this technique ensures that data dependency hazards will not occur, the performance penalty encountered utilizing this technique is substantial.
As a consequence, modern superscalar data processing systems often utilize a so-called “data dependency interlock circuit.” Such circuits contain logic which operates in concert with instruction dispatch circuitry to ensure that an instruction is not dispatched until such time as a result from a preceding instruction which is necessary for correct execution of that instruction has been obtained. The amount of logic required to implement a data dependency interlock circuit is directly proportional to the number of source operands within each instruction. A source operand is a field within an instruction which is utilized to access an operand within a register file, for utilization in execution of that instruction.
While data dependency interlock circuits permit data dependency hazards to be avoided without encountering the substantial performance penalty described above, the design and implementation of data dependency interlock circuits for instructions which include larger numbers of source and destination operands becomes quite complex.
The data dependency hazards which occur with the simultaneous executing of multiple instructions in each processor cycle have also been addressed by utilizing an approach known as “register renaming.” Register renaming is a technique utilized to temporarily place the results of a particular instruction into a register for potential use by later instructions prior to the time the final result from an instruction is placed within a register file. Register renaming is generally accomplished by providing a register file array with extra locations and a pointer arrangement to identify particular physical registers which have been assigned to logical registers. Selected prior art approaches also utilize multiple register file arrays to provide many “read” ports for data or for holding previous results for backup in the case of exceptions.
While this technique provides the ability to simultaneously dispatch and execute multiple instructions where serial execution might otherwise be necessary, a problem exists with the dispatching of instructions to execution units utilizing such techniques. The execution of more than one instruction during a single processor cycle may cause hazards which the processor must handle in a correct manner. One hazard that such processors must be able to handle is the reporting of precise exceptions. That is, the ability to accurately distinguish which instruction in a series of instructions created an exception which must be corrected in order to resume normal processing.
It should therefore be apparent that a need exist for a method and system which permit nonsequential instruction dispatch and execution within a superscalar processor system while supporting precise interrupts by permitting instructions to be executed nonsequentially while assembling results in an application specified ordered sequence.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved method and system for nonsequential instruction dispatch and execution efficiency in a superscalar processor system.
It is yet another object of the present invention to provide an improved method and system for nonsequential instruction dispatch in a superscalar processor system which permits accurate reporting of interrupts and execution.
The foregoing objects are achieved as is now described. The method and system of the present invention permits nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers in an application specific sequential order. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to each destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer or buffers. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an ordered consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buff
Kahle James Allan
Waldecker Donald Emil
Felsman Bradley Vaden Gunter & Dillon, LLP
Follansbee John A.
International Business Machines - Corporation
Salys Casimer K.
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