Method and system for non-linear state based satisfiability

Details Method and system for non-linear state based satisfiability Method and system for non-linear state based satisfiability

2008-05-27

2008-05-27

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07380224

ABSTRACT:
A computerized method and system for solving non-linear Boolean equations is disclosed comprising at least partially solving a Boolean function; developing at least one inference regarding said Boolean function and saving said inference to a state machine; and accessing said inference from said state machine to develop at least one heuristic for determining whether said Boolean function is satisfiable.

REFERENCES:
patent: 5088048 (1992-02-01), Dixon et al.
Chatalic, Philippe, et al.,Multi-Resolution on Compressed Sets of Clauses.
Baher, R. Iris, et al.,Power Optimization of Technology-Dependent Circuits Based on Symbolic Computation of Logic Implications.
Paruthi, Viresh, et al.,Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation(pp. 459-464).
Wilson, Chris, et al.,Reliable Verification Using Symbolic Simulation with Scalar Values.
Kalla, Priyank, et al.,A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm, Technical Report: TR-CSE-99-6.
Gupta, Aarti, et al.,Fast Error Diagnosis for Combinational Verification.
Prasad, Mukul R., et al.,Why is ATPG easy?.
Bryant, Randal E., et al.,Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions.
Biere, Armin, et al.,Symbolic Model Checking without BDDs; Submitted for TACAS (1999).
Tragoudas, S. et al.,Functional ATPG for Delay Faults.
Nam, Gi-Joon, et al.,Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT(pp. 167-175).
Bollig, et al.,Hierarchy Theorems for kOBDDs and kIBDDs.
Wood, R. Glenn, et al.,FPGA Routing and Routability of Estimation Via Boolean Satisfiability.
Gupta, Aarti, et al.,Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking(pp. 222 225).
Cyrluk, David et al.,An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors.
Takagi, Kazuyoshi, et al,Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses, IEICE Trans. Fundamentals E80:4, pp. 663-669 (Apr. 1997).
Kawakubo, Kasuo, et al.,Formal Verification of Self-Testing Properties of Combinational Circuits, Proceedings of ATS '96, pp. 119 122.
Puri, Ruchir, et al.,A BDD SAT solver for satisfiability testing: An industrial case study, Annals of Mathematics and Artificial Intelligence 17, pp. 315-337 (1996).
Groote, Jan F,Hiding Propositional Constants in BDDs.
Nakaoka, Toshihiro, et al.,A Verification Algorithm for Logic Circuits with Internal Variables, pp. 1920-1923.
Ashar, Pranav, et al.,Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams(pp. 259 264.
Burch, J.R., et al.,Symbolic Model Checking: 1020States and Beyond, pp. 1-33.
Bryant, Randal E., et al.,Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic(May 1999).
Biere, A., et al.,Symbolic Model Checking using SAT procedures instead of BDDs.

Affiliated with

Also associated with

Rating

Method and system for non-linear state based satisfiability does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for non-linear state based satisfiability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for non-linear state based satisfiability will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2766805