Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-08-13
2001-01-16
Kizou, Hassan (Department: 2738)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S422000, C370S535000
Reexamination Certificate
active
06175567
ABSTRACT:
CLAIM FOR PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for METHOD AND SYSTEM FOR MULTIPLEXING/DEMULTIPLEXING ASYNCHRONOUS TRANSFER MODE INTERPROCESSOR COMMUNICATION (ATM IPC) CELL IN EXCHANGE earlier filed in the Korean Industrial Property Office on the 14th of August 1996, and there duly assigned Serial No. 33620/1996, a copy of which application is annexed hereto.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an asynchronous transfer mode (ATM) exchange, and more particularly, relates to a system for multiplexing/demultiplexing an ATM interprocessor communication cell (IPC) in an ATM exchange.
2. Related Art
Generally, ATM is a specific packet-oriented transfer mode using an asynchronous time division multiplexing technique where both line switching and packet switching are unified and many pieces of information such as voice, data, and pictures are organized in fixed-sized blocks, called cells. ATM can operate as both a packet exchange system and a circuit exchange system in one transmission mode for efficiently embodying both high speed and wide band communication networks. For this reason, ATM is a target transfer mode solution for implementing a broadband integrated services digital network (B-ISDN) because it offers an effective information channel management based upon virtual path and virtual channel identifiers (“VPI” and “VCI”) placed in a header of each cell which facilitates the use of a multiplex, de-multiplex and exchange of digital information, and serves to decrease the costs of broad-band communication network facilities because of its flexibility in a bandwidth distribution.
Conventionally, there are a variety of ATM switching networks. Exemplary configurations are disclosed, for example, in U.S. Pat. No. 5,189,668 for ATM Switch And ATM Multiplexer issued to Takatori et al, U.S. Pat. No. 5,119,369 for Packet Switch Communication Network Using Packet Using Virtual Channel Identifiers issued to Tanabe et al., U.S. Pat. No. 5,214,642 for ATM Switching System And Adaption Processing Apparatus issued to Kunimoto, U.S. Pat. No. 5,258,977 for Switching Network For An Asynchronous Time Division Multiplex Transmission System issued to Wolker et al., U.S. Pat. No. 5,287,349 for ATM Exchange System issued to Hyodo et al., U.S. Pat. No. 5,339,310 for Switching Apparatus For Switched Network Of Asynchronous Transfer Mode issued to Taniguchi, U.S. Pat. No. 5,499,238 for Asynchronous Transfer Mode (ATM) Multiplexing Process Device And Method Of The Broadband Integrated Service Digital Network Subscriber Access Apparatus issued to Shon, U.S. Pat. No. 5,455,820 for Output-Buffer Switch For Asynchronous Transfer Mode issued to Yamada, U.S. Pat. No. 5,513,178 for Cell Multiplexing Apparatus In ATM Network issued to Tanaka., U.S. Pat. No. 5,519,707 for Multiplexing Of Communication Services On A Virtual Service Path IN An ATM Network Or The Like issued to Subramanian et al., and U.S. Pat. No. 5,594,723 for ATM Information System And Multiplexer For Assigning And Controlling Access Time issued to Tibi. An ATM multiplexer/demultiplexer can be inserted between subscriber lines and the ATM switching network for switching ATM cells as disclosed in U.S. Pat. No. 5,448,557 for ATM Multiplexer/Demultiplexer For Use In An ATM Switching System issued to Hauber, or adjacent to the ATM switching network as disclosed in U.S. Pat. No. 5,365,519 for ATM Switching System Connectable To I/O Links Having Different Transmission Rates issued to Kozaki et al., and U.S. Pat. No. 5,623,493 for Multiplexer Demultiplexer Switching Device And Network Adapter issued to Kagemoto.
For the interprocessor communication (IPC) of an ATM exchange as disclosed, for example, in U.S. Pat. No. 5,550,978 for Multiprocessor System Having Switches For Routing Cells In Parallel Among Processors by Splitting Data Into Blocks Having Numbers Of Cells Equals To Processor Bus Width issued to Takahashi et al., however, one IPC cell transceiver is required for each processor connected to the ATM exchange. As the capacity of an ATM switch increases, the number of processors increases and consequently the number of IPC cell transceivers. Moreover, since one ATM switch port per IPC cell transceiver is needed, the number of the ATM switch ports increases. Therefore, a large number of hardware is required, and it is difficult to efficiently manage resources.
SUMMARY OF THE INVENTION
Accordingly, it is therefore an object of the present invention to provide a system for multiplexing or demultiplexing an interprocessor communication (IPC) cell in an ATM exchange.
It is another object of the invention to provide a system for efficiently managing new resources by multiplexing or demultiplexing an interprocessor communication (IPC) cell in an ATM exchange.
These and other objects of the invention can be achieved by a system for multiplexing/demultiplexing an ATM IPC cell in an ATM exchange which includes an IPC cell multiplexing/demultiplexing circuit connected between an operation and maintenance processor, first to third subscriber control processors and an ATM switch. The IPC cell multiplexing/demultiplexing circuit reads a virtual path identifier (VPI) value of an IPC cell received from the ATM switch to select a processor to transfer the cell to, transfers the received IPC cell to the corresponding processor at a speed of 100 Mbps, and multiplexes the IPC cell received from a specific processor among the operation and maintenance processor and the first to third subscriber control processors.
The present invention is more specifically described in the following paragraphs by reference to the drawings attached only by way of example.
REFERENCES:
patent: 5119369 (1992-06-01), Tanabe et al.
patent: 5189668 (1993-02-01), Takatori et al.
patent: 5214642 (1993-05-01), Kunimoto et al.
patent: 5258977 (1993-11-01), Wolker et al.
patent: 5287349 (1994-02-01), Hyodo et al.
patent: 5303236 (1994-04-01), Kunimoto et al.
patent: 5339310 (1994-08-01), Taniguchi
patent: 5365519 (1994-11-01), Kozaki et al.
patent: 5448557 (1995-09-01), Hauber
patent: 5487063 (1996-01-01), Kakuma et al.
patent: 5499238 (1996-03-01), Shon
patent: 5504742 (1996-04-01), Kakuma et al.
patent: 5513178 (1996-04-01), Tanaka
patent: 5519707 (1996-05-01), Subramanian et al.
patent: 5548588 (1996-08-01), Ganmukhi et al.
patent: 5550978 (1996-08-01), Takahashi et al.
patent: 5594723 (1997-01-01), Tibi
patent: 5612695 (1997-03-01), Ueda
patent: 5623493 (1997-04-01), Kagemoto
patent: 5896371 (1999-04-01), Kobayashi et al.
Bushnell , Esq. Robert E.
Kizou Hassan
Samsung Electronics Co,. Ltd.
Tsegaye Saba
LandOfFree
Method and system for multiplexing/demultiplexing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for multiplexing/demultiplexing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for multiplexing/demultiplexing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2522279