Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1999-01-15
2001-06-26
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S120000, C710S120000
Reexamination Certificate
active
06253268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates in general to interfaces for communicating data in an integrated circuit environment, and in particular to a method and system for communicating data over shared bus lines using multiple interfaces.
2. Description of Related Art
Communications between integrated circuits and other devices in many applications use the Intelligent Interconnection Communication (I
2
C), or Inter-IC, serial interface developed by Philips Semiconductors. In the telecommunications industry, for example, mobile telephones frequently use the I
2
C interface protocol to communicate between the base band controller, which is typically an application specific integrated circuit (ASIC), and the LCD module. Other devices within mobile telephones also use the I
2
C interface protocol to receive data (including commands) from, and transmit data to, the base band controller.
However, because the I
2
C interface is subject to certain patent protections, developers of LCD drivers and other drivers must normally obtain a license to be able to manufacture drivers that support the I
2
C interface protocol. As a result, the supply of off-the-shelf drivers that support I
2
C is often limited. With the ever shortening development cycles in the mobile telecommunications industry and other industries that use the I
2
C interface protocol, there is not always time to custom develop a driver that supports I
2
C.
On the other hand, many of the existing off-the-shelf drivers support a serial point-to-point interface protocol that uses four lines: a data line, a clock line, a line specifying either command data or display data, and a chip select line. One alternative to having to custom develop a driver that supports I
2
C is to construct the base band controller or other ASIC to support both the I
2
C interface protocol and the serial point-to-point interface protocol. Additional devices can then be added using either a driver that supports the I
2
C interface protocol or a driver that supports a serial point-to-point interface protocol, depending on availability, cost, and functional considerations. To support two interfaces, however, four extra I/O pins (for each of the four serial point-to-point interface lines) are needed on the base band controller. This requirement is problematic because I/O pins add expense and require additional space. In addition, while systems that support multiple interface protocols using shared bus lines have been suggested, such systems are complex, inflexible, and difficult to implement.
There is a need, therefore, for a simplified, flexible method and system that allows communications between an integrated circuit and one or more other devices using one of a plurality of available interface protocols via shared bus lines. The system should include a minimal number of I/O pins. Such a method and system would permit, for example, the use of a driver that supports I
2
C, when available, or a serial point-to-point driver, if an I
2
C driver is not available or if different capabilities are desired. In addition, such a method and system would permit the integrated circuit to selectively use different interface protocols depending on which protocol is supported by the device with which the integrated circuit is communicating.
SUMMARY OF THE INVENTION
The present invention comprises a method and system for communicating data between an integrated circuit and a plurality of peripheral devices. The integrated circuit communicates with a first one of the peripheral devices using an I
2
C interface protocol and communicates with a second peripheral device using some other interface protocol. Both interface protocols, however, share the same data bus and clock bus, thereby reducing the number of pins needed on the integrated circuit.
Communications between the integrated circuit and the first peripheral device are achieved in accordance with standard I
2
C interface protocols. Thus, to communicate with the first peripheral device, the integrated circuit transmits via the shared data bus a unique I
2
C start condition followed by an address identifying the first peripheral device. The integrated circuit then transmits, and the first device receives, the data intended for the first device using the shared data bus. The first device then replies with an acknowledge bit after each byte received. At the end of the data transmission, a unique stop condition is transmitted. During such communications using the I
2
C interface protocol, the integrated circuit maintains a high voltage on a chip select bus. This high voltage on the chip select bus serves to inform the second peripheral device that I
2
C communications are ongoing and prevents the second device from interfering with such communications.
On the other hand, when communications via the I
2
C interface are not ongoing, communications with the second peripheral device can be initiated. After a stop condition is sent over the shared data bus, the integrated circuit generates another I
2
C start condition. This time, however, the start condition is followed by an address that is not used by the first peripheral device (or by any other attached I
2
C device), which causes the first device (and any other attached I
2
C devices) to enter into an inactive state. Then, by removing the high voltage on the chip select bus, the second device is activated and data communications between the integrated circuit and the second device, via the shared data bus, can be performed, provided that none of the attached devices inadvertently transmit a start or stop condition, which might reactivate the attached I
2
C devices. Once such data communications are complete, the integrated circuit generates a stop condition on the shared data bus, causing the attached I
2
C devices to again begin listening for a start condition. Thus, communications using other interface protocols can be interlaced with I
2
C communications without requiring an additional data bus and clock bus, while simultaneously avoiding conflicts between the two or more interfaces.
REFERENCES:
patent: 4779092 (1988-10-01), Takao
patent: 4972432 (1990-11-01), Wilson et al.
patent: 5276857 (1994-01-01), Hartung et al.
patent: 5376928 (1994-12-01), Testin
patent: 5386579 (1995-01-01), Bourekas et al.
patent: 5568471 (1996-10-01), Hershey et al.
patent: 5621901 (1997-04-01), Morriss et al.
patent: 5710908 (1998-01-01), Man
patent: 5771360 (1998-06-01), Gulick
patent: 5793993 (1998-08-01), Broedner et al.
patent: 5794014 (1998-08-01), Shetty et al.
patent: 5852406 (1998-12-01), Edde et al.
patent: 5884044 (1999-03-01), Marsanne et al.
patent: 6026007 (2000-02-01), Jigour et al.
patent: 0 619 548 A1 (1994-10-01), None
patent: 2 288 954 (1995-11-01), None
patent: WO 98/15105 (1998-04-01), None
Phillips Semiconductors1995 update; “The I2C-bus and how to use it (including specifications)”; Apr. 1995.
EPO Standard Search Report, Mailed Jul. 5, 1999.
Björkengren Ulf Christian
Khullar Anders
Uggmark Johan Georg Michael
Jenkens & Gilchrist P.C.
Ray Gopal C.
Telefonaktiebolaget L M Ericsson (publ)
LandOfFree
Method and system for multiplexing a second interface on an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for multiplexing a second interface on an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for multiplexing a second interface on an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2462579