Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-14
2004-01-06
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06674121
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic circuits and applications and method of manufacture thereof. More specifically, the invention relates to a hybrid transistor circuit incorporating charge storage molecules.
BACKGROUND OF THE INVENTION
The discussion of any work, publications, sales, or activity anywhere in this submission, including in any documents submitted with this application, shall not be taken as an admission by the inventors that any such work constitutes prior art. The discussion of any activity, work, or publication herein is not an admission that such activity, work, or publication was known in any particular jurisdiction.
The great majority of electronic devices in use today employ solid-state transistors as a chief building block. In digital devices, and in many analog devices, these transistors are field-effect transistors (FETs) of various types and used in various configurations.
One important goal in the development of electronic devices is miniaturization. The smaller the individual transistor device, the more complex and powerful the electronic circuit that can be constructed in a given area. However, an alternative to miniaturization is multi-mode operation. Thus, if a transistor with just two state operation is replaced with a transistor with four or eight state operation, even of the same size, again more complex and highly functional circuits can be constructed in a given region.
A further goal in the development of electronic devices is devices that can retain state when power is OFF. This is particularly true for devices such as memory elements used in cell-phones. A device widely used in such appliances is FLASH memory. FLASH memory, as known in the art, commonly employs one or more floating gate FETs to hold charge.
However, there are at least two drawbacks to commonly used FLASH memories. One is that current manufacturing technologies are expected to provide limited ability to shrink memory cells thereby limiting memory density. The other is that many FLASH memory designs require high-power (as much as 15 V) to write to the memory.
Multibit storage has been proposed for various types of FLASH memory cells in order to increase memory density. However, most current approaches have been accompanied by many problems, such as: (1) limited precision in reading, i.e., the inability to detect the current with sufficiently high accuracy and high speed; (2) inaccurate writing, i.e., the inability to place the right amount of charge on the floating gate to obtain the target V
T
(threshold voltage) value; (3) unreliability due to lack of maintenance of adequate spacing between adjacent stored levels in a memory cell for sufficiently long time intervals.
In a conventional FLASH, the threshold voltage depends analogically on the amount of charge stored in the floating gate and hence the I
DS
can be changed over a large range of values. In such devices, if multiple bits are desired, the &Dgr;
IDS
between states becomes smaller which in turn makes the sensing and writing prone to errors. To avoid this problem, the &Dgr;
IDS
between bits can be increased; however, this is generally at the cost of higher voltages, which can degrade reliability and make devices more difficult to operate.
Single-electron memories have recently been investigated for replacement of DRAM memories. These devices consist of a transistor where small metal or semiconductor islands are placed in the SiO
2
matrix. These islands exhibit coulomb blockade oscillations and can therefore be used as multi-value memories. Although several single-electron memory approaches have been reported, they all require that the islands be in the nanoscale regime in order to observe oscillations. Because all the reported devices are fabricated using non-manufacturable shrinking techniques, they all suffer from non-reproducibility, owing to the variation in the island size from device to device. The variation of size, orientation, and charge state may ultimately limit the viability of using single-electron charging for memory applications. Moreover, these single-electron charging devices still require high voltages (generally >15 V) to store multiple levels.
Patent References
Various strategies have been proposed for constructing memory devices using molecular electrical storage elements, among them those discussed in the below indicated patents and other publications:
U.S. Pat. No. 6,272,038; High-density non-volatile memory devices incorporating thiol-derivatized porphyrin trimers
U.S. Pat. No. 6,212,093; High-density non-volatile memory devices incorporating sandwich coordination compounds
U.S. Pat. No. 6,208,553; High density non-volatile memory device incorporating thiol-derivatized porphyrins.
Strategies and background techniques for using a dummy gate in constructing a semiconductor device are discussed in:
U.S. Pat. No. 5,960,270; Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions.
Charge Storage References
[1] K. M. Roth, N. Dontha, R. B. Dabke, D. T. Gryko, C. Clausen, J. S. Lindsey, D. F. Bocian, and Werner G. Kuhr, “Molecular Approach toward Information Storage Based on the Redox Properties of Porphyrins in Self-Assembled Monolayers,” J. Vac. Sci. Technol. B 2000, 18, 2359-2364.
[2] D. T. Gryko, C. Clausen, K. M. Roth, N. Dontha, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey “Synthesis of “Porphyrin-Linker-Thiol” Molecules with Diverse Linkers for Studies of Molecular-Based Information Storage,” J. Org. Chem. 2000, 65, 7345-7355.
[3] D. T. Gryko, F. Zhao, A. A. Yasseri, K. M. Roth, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey “Synthesis of Thiol-Derivatized Ferrocene-Porphyrins for Studies of Multibit Information Storage,” J. Org. Chem. 2000, 65, 7356-7362.
[4] C. Clausen, D. T. Gryko, R. B. Dabke, N. Dontha, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey, “Synthesis of Thiol-Derivatized Porphyrin Dimers and Trimers for Studies of Architectural Effects on Multibit Information Storage,” J. Org. Chem. 2000, 65, 7363-7360.
[5] C. Clausen, D. T. Gryko, A. A. Yasseri, J. R. Diers, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey, “Investigation of Tightly Coupled Porphyrin Arrays Comprised of Identical Monomers for Multibit Information Storage,” J. Org. Chem. 2000, 65, 7371-7378.
[6] J. Li, D. Gryko R. B. Dabke, J. R. Diers, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey “Synthesis of Thiol-Derivatized Europium Porphyrinic Triple-Decker Sandwich Complexes for Multibit Molecular Information Storage,” J. Org. Chem. 2000, 65, 7379-7390.
[7] D. T. Gryko, P. C. Clausen, and J. S. Lindsey, “Thiol-Derivatized Porphyrins for Attachment to Electroactive Surfaces,” J. Org. Chem. 1999, 64, 8635-8647.
[8] D. Gryko, J. Li, J. R. Diers, K. M. Roth, D. F. Bocian, W. G. Kuhr, and J. S. Lindsey, “Studies Related to the Design and Synthesis of a Molecular Octal Counter,” J. Mater. Chem., 2001, Vol. 11, p. 1162-1180.
[9] K. M. Roth, J. S. Lindsey, D. F. Bocian, and W. G. Kuhr, “Open Circuit Potential Amperometry and Voltammetry of Surface-Bound Redox-Active Species,” Langmuir, submitted.
[10] B. Eitan and A. Roy, In Flash Memories, P. Cappalletti, Ed.; Kluwer Academic Publishers: Boston, 1999.
[11] K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, T. Hashimoto, T. Kobayashi, T. Kure and K. Seki, “Single-Electron Memory for Giga-to-Tera Bit Storage,” Proc. IEEE 1999, 87, 633-651.
[12] Misra et al., U.S. Pat. No. 5,960,270.
[13] A. Chatterjee et al., “Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process,” IEDM Tech. Dig. 1997, 821-824.
[14] J. M. Buriak, “Organometallic Chemistry on Silicon Surfaces: Formation of Functional Monolayers Bound Through Si-C Bonds,” Chem. Commun. 1999, 1051-1060.
[15] J. A. Haber, I. Lauermann, D. Michalak, T. P. Vaid, and N. S. Lewis, “Electrochemical and Electrical Behavior of (111)-Oriented Si
Bocian David F.
Kuhr Werner G.
Lindsey Jonathan S.
Misra Veena
LeBlanc Stephen J.
Pham Long
Quine Intellectual Property Law Group P.C.
The Regents of the University of California
Weiss Howard
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