Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-08
2008-01-08
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11232747
ABSTRACT:
The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “Π”-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.
REFERENCES:
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5617325 (1997-04-01), Schaefer
patent: 5841672 (1998-11-01), Spyrou et al.
patent: 5875114 (1999-02-01), Kagatani et al.
patent: 6080201 (2000-06-01), Hojat et al.
patent: 6189131 (2001-02-01), Graef et al.
patent: 6317861 (2001-11-01), Hasegawa
patent: 6463567 (2002-10-01), Kozai
patent: 6532577 (2003-03-01), Mbouombouo et al.
patent: 6581195 (2003-06-01), Tanaka
patent: 6665845 (2003-12-01), Aingaran et al.
patent: 6880141 (2005-04-01), Tetelbaum
patent: 2002/0056070 (2002-05-01), Tanaka
patent: 2003/0169059 (2003-09-01), Bodenstab
patent: 2004/0111688 (2004-06-01), Lee et al.
patent: 2004/0216062 (2004-10-01), Fan
Burstein et al., “Timing-influenced layout design”, IBM Technical Disclosure Bulletin, vol. 28, No. 11, Apr. 1986.
Luitjen, “Time-driven CMOS gate placement”, IBM Technical Disclosure Bulletin, vol. 33, No. 1A, Jun. 1990.
Amit Niv
Bustin Ronit
Goren Lidor
Heymann Omer
Leibowitz Moshe
Do Thuan
Erez Suzanne
International Business Machines - Corporation
LandOfFree
Method and system for modeling wiring routing in a circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for modeling wiring routing in a circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for modeling wiring routing in a circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3921108