Method and system for modeling variation of circuit...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11014096

ABSTRACT:
A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit parameter values. This delay equation calculates the delay for any value in the circuit parameter range. Similar methodology is used to model simultaneous variation of two circuit parameters. The cell is characterized at just six circuit parameter pairs to interpolate the delay equation for any circuit parameter pair in the characterized ranges. This methodology can be extended to accommodate variation of multiple circuit parameters using similar interpolation techniques.

REFERENCES:
patent: 5675502 (1997-10-01), Cox
patent: 5841672 (1998-11-01), Spyrou et al.
patent: 6047247 (2000-04-01), Iwanishi et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6314546 (2001-11-01), Muddu
patent: 6476635 (2002-11-01), Rahim et al.
patent: 6721929 (2004-04-01), Li et al.
patent: 6894547 (2005-05-01), Takahashi
patent: 2004/0249588 (2004-12-01), Shimazaki et al.
Daga, J.M. et al. “Temperature Effect on Delay for Low Voltage Applications” Proceedings of the Conference on Design, Automation and Test in Europe (date '98), 1998, 6 pgs.
Kahng, A.B. et al. “Efficient Gate Delay Modeling for Large Interconnect Loads” Proceedings of the 1997 International Conference on Computer Design (ICCD'97) VLSI in Computers and Processors, Oct. 12-15, 1997, pp. 532-541.
Shepard, K.L. “Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits” Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC-96), Feb. 6-7, 1996, pp. 202-207.

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