Method and system for minimizing memory access latency in a...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C718S102000, C718S103000, C709S201000, C709S216000, C709S217000, C709S223000, C709S226000, C712S028000, C713S001000, C713S002000, C713S100000

Reexamination Certificate

active

10328440

ABSTRACT:
A computer system includes a plurality of nodes coupled together wherein each node may comprise a processor and memory. The system may also include a plurality of software objects usable by any of the nodes. Each object may be provided to, and stored in, the memory of the node that most frequently uses the object.

REFERENCES:
patent: 4914570 (1990-04-01), Peacock
patent: 5442771 (1995-08-01), Filepp et al.
patent: 5517662 (1996-05-01), Coleman et al.
patent: 5574944 (1996-11-01), Stager
patent: 5594910 (1997-01-01), Filepp et al.
patent: 5687370 (1997-11-01), Garst et al.
patent: 5758072 (1998-05-01), Filepp et al.
patent: 5924116 (1999-07-01), Aggarwal et al.
patent: 5940621 (1999-08-01), Caldwell
patent: 6026415 (2000-02-01), Garst et al.
patent: 6065058 (2000-05-01), Hailpern et al.
patent: 6085193 (2000-07-01), Malkin et al.
patent: 6088758 (2000-07-01), Kaufman et al.
patent: 6092098 (2000-07-01), Araki et al.
patent: 6182123 (2001-01-01), Filepp et al.
patent: 6304884 (2001-10-01), Garst et al.
patent: 6421713 (2002-07-01), Lamparter
patent: 6651141 (2003-11-01), Adrangi
patent: 6779030 (2004-08-01), Dugan et al.
patent: 7024450 (2006-04-01), Deo et al.
patent: 7054900 (2006-05-01), Goldston
patent: 2002/0073167 (2002-06-01), Powell et al.
patent: 2002/0091763 (2002-07-01), Shah et al.
patent: 2002/0133537 (2002-09-01), Lau et al.
patent: 2002/0165939 (2002-11-01), Terribile
patent: 2003/0018960 (2003-01-01), Hacking et al.
Kopp, Carlo, “Proxies and Performance,” Dec. 2000, Carlo Kopp's Systems Publications, pp. 1-8.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for minimizing memory access latency in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for minimizing memory access latency in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for minimizing memory access latency in a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3891390

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.