Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-02-26
2010-06-08
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S002000, C714S003000, C714S005110, C714S006130, C714S006130, C714S025000, C714S026000, C714S030000, C714S042000, C714S048000, C714S710000, C714S711000, C714S719000, C714S723000, C714S733000, C714S734000, C714S736000, C365S201000
Reexamination Certificate
active
07734966
ABSTRACT:
The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.
REFERENCES:
patent: 5568437 (1996-10-01), Jamal
patent: 6044481 (2000-03-01), Kornachuk et al.
patent: 6243307 (2001-06-01), Kawagoe
patent: 6367042 (2002-04-01), Phan et al.
patent: 6370661 (2002-04-01), Miner
patent: 6381715 (2002-04-01), Bauman et al.
patent: 6404684 (2002-06-01), Arimoto et al.
patent: 6408401 (2002-06-01), Bhavsar et al.
patent: 6486493 (2002-11-01), Arimoto et al.
patent: 6493647 (2002-12-01), Chiang et al.
patent: 6493839 (2002-12-01), Miner
patent: 6496947 (2002-12-01), Schwarz
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 6721904 (2004-04-01), Ernst et al.
patent: 6725403 (2004-04-01), Schmoelz
patent: 6738938 (2004-05-01), Nadeau-Dostie et al.
patent: 6862704 (2005-03-01), Miner
patent: 6904552 (2005-06-01), Cowles
patent: 6993696 (2006-01-01), Tanizaki et al.
patent: 7010736 (2006-03-01), Teh et al.
patent: 2001/0056557 (2001-12-01), Kawagoe et al.
patent: 2002/0066057 (2002-05-01), Daehn
patent: 2002/0087926 (2002-07-01), Kuhn et al.
patent: 2002/0194558 (2002-12-01), Wang et al.
patent: 2003/0005353 (2003-01-01), Mullins et al.
patent: 2003/0097626 (2003-05-01), Tseng et al.
patent: 2004/0093540 (2004-05-01), Adams et al.
patent: 2004/0133826 (2004-07-01), Zhu et al.
patent: 1031994 (2000-08-01), None
Lee Winston
Liou Chorng-Lii
Wu Albert
Marvell International Ltd.
Trimmings John P
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