Method and system for memory partitioning

Details Method and system for memory partitioning Method and system for memory partitioning

2011-01-04

2011-01-04

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000

Reexamination Certificate

active

07865796

ABSTRACT:
Systems and methods for interleaver and deinterleaver memory partitioning optimize data rate and error correction. Optimized memory allocation is important in systems that support bi-directional communication over multiple data paths. By using path-specific information such as impulse noise protection and data rate, memory may be dynamically partitioned to optimize the capacity in individual data paths.

REFERENCES:
patent: 6151690 (2000-11-01), Peeters
patent: 6363026 (2002-03-01), Su et al.
patent: 6546509 (2003-04-01), Starr
patent: 7408999 (2008-08-01), Xue et al.
patent: 2006/0107170 (2006-05-01), Deczky

Affiliated with

Also associated with

Rating

Method and system for memory partitioning does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for memory partitioning, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for memory partitioning will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2706382