Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-09-27
2003-06-03
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185240, C365S185140
Reexamination Certificate
active
06574158
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices, and more particularly to erasable programmable read-only memory.
BACKGROUND OF THE INVENTION
An Erasable Programmable Read-Only Memory (EPROM) provides a convenient approach for non-volatile storage of information. The competitive EPROM market continually poses a challenge for memory manufacturers to produce these solid-state memories cost-effectively. During testing of the EPROMs, a capability of reading out threshold voltages of unprogrammed or erased EPROM cells is needed to improve yield.
With conventional EPROMs, the threshold voltages may not be precisely measured. That is, only an estimate of whether the threshold is below a source voltage (VDD) can be made. Actual voltages cannot be measured economically. Specifically, because the unprogrammed thresholds are very low (for example, 0.9 v to 1.1 v), the associated read circuits, which operate at higher normal operating voltages (e.g., 3.3 v or 5.0 v), are not read such low threshold voltages. For example, voltage thresholds are on the order of 1.0 v. To read such low voltage values, the read circuit would be required to operate at 1.0 v. Therefore, there is an inability to verify whether an EPROM is erased completely or partially.
Traditionally, complex circuitry is added in the memory device to read the threshold voltages. A number of drawbacks attend such an approach. The additional complexity translates into higher manufacturing costs. Also, the added circuitry may require increased power consumption.
Therefore, there is a need for a simplified approach to measuring EPROM thresholds. There is also a need to improve yield of the EPROMs in a cost-effective manner.
SUMMARY OF THE INVENTION
These and other needs are addressed by the present invention in which an approach is provided to test an erasable programmable read-only memory (EPROM) cell for a threshold voltage. A circuit applies a voltage that is lower (in magnitude) than a source voltage associated with a read operation to drive the EPROM cell. For example, the voltage is in the range of about 0.9 v to about 1.1 v, while the source voltage is about 3.3 v or 5.0 v. A read logic operates using this source voltage. Under a normal read operation, a switch, which is coupled to the EPROM cell, drives the EPROM cell according to the source voltage. In a threshold read operation, the switch is disabled to permit a different voltage to be applied to the gate of the EPROM cell. In this manner, the source voltage is prevented from being applied to the gate. The circuit, which may be a potential divider circuit or a fixed difference circuit, generates the voltage to represent, respectively, a fixed ratio of the source voltage or a fixed difference with the source voltage. A signal from the EPROM cell is readout when the voltage is applied to the EPROM cell to calculate the threshold voltage. Under this arrangement, the threshold voltage of unprogrammed or erased EPROM cell can be determined accurately without complex circuitry.
According to one aspect of the present invention, a method for testing an EPROM cell for a threshold voltage is disclosed. The method includes applying a voltage lower than another voltage that is associated with a read operation to drive the EPROM cell. The method also includes reading out a signal from the EPROM cell when the voltage is applied to the EPROM cell.
According to another aspect of the present invention, a memory device is disclosed. The device includes an EPROM cell having a gate. The device also includes a circuit that is coupled to the gate of the EPROM cell and is configured to generate a voltage lower than another voltage associated with a read operation. A signal is readout from the EPROM cell when the voltage is applied to the EPROM cell.
In yet another aspect of the present invention, a memory device is disclosed. The device includes an EPROM cell. Additionally, the device includes means for applying a voltage lower than another voltage associated with a read operation to drive the EPROM cell. A signal from the EPROM cell is readout when the voltage is applied to the EPROM cell.
Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various obvious respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.
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Cypress Semiconductor Corp.
Ditthavong & Carlson P.C.
Lam David
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