Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
1998-07-14
2001-04-17
Miska, Vit (Department: 2859)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C368S118000, C368S120000, C324S617000, C324S763010, C324S765010, C714S733000
Reexamination Certificate
active
06219305
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and circuit configurations for measuring signal propagation delays, and in particular for measuring signal propagation delays through integrated circuits.
BACKGROUND
Integrated circuits (ICs) are the cornerstones of myriad computational systems, such as personal computers and communications networks. Purchasers of such systems have come to expect significant improvements in speed performance over time. The demand for speed encourages system designers to select ICs that guarantee superior speed performance. This leads IC manufacturers to carefully test the speed performance of their designs.
FIG. 1
depicts a conventional test configuration
100
for determining the signal propagation delay of a test circuit
110
in a conventional IC
115
. A tester
120
includes an output lead
125
connected to an input pin
130
of IC
115
. Tester
120
also includes an input line
135
connected to an output pin
140
of IC
115
.
Tester
120
applies an input signal to input pin
130
and measures how long the signal takes to propagate through test circuit
110
to output pin
140
. The resulting time period is the timing parameter for the path of interest. Such parameters are typically published in literature associated with particular ICs or used to model the speed performance of circuit designs that employ the path of interest.
Conventional test procedures are problematic for at least two reasons. First, many signal paths within a given IC cannot be measured directly, leading to some speculation as to their true timing characteristics. Second, testers have tolerances that can have a significant impact on some measurements, particularly when the signal propagation time of interest is short. For example, if the tester is accurate to one nanosecond and the propagation delay of interest is measured to be one nanosecond, the actual propagation delay might be any time between zero and two nanoseconds. In such a case the IC manufacturer would have to list the timing parameter as two nanoseconds, the worst-case scenario. If listed timing parameters are not worst-case values, some designs may fail. Thus, IC manufacturers tend to add relatively large margins of error, or “guard bands,” to ensure that their circuits will perform as advertised. Unfortunately, this means that those manufacturers will not be able to guarantee their full speed performance, which could cost them customers in an industry where speed performance is paramount.
Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that, by determining the states of various programming points, define how the CLBs, interconnections, and IOBs are configured.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of these and other delay-inducing elements make timing predictions particularly difficult. FPGA designers use circuit models, called “speed files,” that include delay values or resistance and capacitance values for the various delay-inducing elements that can be combined to form desired signal paths. These circuit models are then used to predict circuit timing for selected FPGA configurations.
Manufacturers of ICs, including FPGAs, would like to guarantee the highest speed timing specifications possible without causing FPGAs to fail to meet timing specifications. More accurate measurements of circuit timing allow IC manufacturers to use smaller guard bands to ensure correct device performance, and therefore to guarantee higher speed performance. There is therefore a need for a more accurate means of characterizing IC speed performance.
SUMMARY
The present invention addresses the need for an accurate means of characterizing IC speed performance. The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include a majority of the requisite test circuitry.
In accordance with the invention, a PLD is configured to implement a free-running ring oscillator within the elements of the PLD to be tested. That is, the PLD is programmed to form a loop through PLD elements to be tested, with an odd number of inversions in the loop so that a signal switches on every cycle through the loop. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions, or edges, on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. The average period of the oscillator is then related to the average signal propagation delay through the test circuit.
Signal paths often exhibit different propagation delays for falling and rising edges, due, for example, to unbalanced driver circuits. The trouble with providing average propagation delays is that the worst-case delay is greater than the average. Consider, for example, the case where a signal path delays falling edges by 2 nanoseconds and rising edges by 3 nanoseconds. The average, 2.5 nanoseconds, is shorter than the worst-case delay associated with rising edges. Unfortunately, the average delay does not indicate whether the delays associated with falling and rising edges are different. Thus, when only the average delay is being measured, a conservative guard band must be added to the average delay.
Another embodiment of the invention reduces the requisite guard band by providing more accurate delay measurements. This embodiment includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC manufacturers to minimize the guard band and consequently guarantee higher speed performance.
In order to determine the durations of the high and low levels of the test signal, a sample clock signal is provided to count in separate counters the sample clock cycles that occur in the high and low portions of the test clock signal oscillating through the test circuit. If the test clock signal is phase locked with the sample-clock signal, the duty cycle calculated by counters that measure high and low parts of the signal may be incorrect. To overcome this problem, the sample clock signal is phase shifted periodically, preferably in a random or pseudo-random manner.
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“The Programmable Logic Data Book,” 1998, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-5 to 4-40.
“Signal Delay in RC
Chung Daniel
Conn Robert O.
Kingsley Christopher H.
Patrie Robert D.
Wells Robert W.
Behiel Arthur J.
Miska Vit
Xilinx , Inc.
Young Edel M.
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