Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Patent
1996-03-05
1999-11-02
Butler, Dennis M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
713600, 710 60, G06F 104
Patent
active
059789271
ABSTRACT:
In a data bus environment where a host device and a plurality of other devices are connected to the bus, the time required for the first and the last device to respond to a host request is measured. Once the time required between the first and the last response is known, then a read/write window time can be minimized thereby increasing the speed of communication over the data bus.
REFERENCES:
patent: 4930093 (1990-05-01), Houser et al.
patent: 5432468 (1995-07-01), Moriyama et al.
Bunsey, Jr. David A.
Curry Stephen M.
Little Wendell L.
Butler Dennis M.
Dallas Semiconductor Corporation
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