Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-30
2008-12-09
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07464348
ABSTRACT:
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution.
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Landry Phuong Ha-Uyen
Lockman Tyler J.
Cadence Design Systems Inc.
Dinh Paul
Vista IP Law Group LLP
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