Method and system for mapping source elements to destination...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07464348

ABSTRACT:
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution.

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patent: 6691296 (2004-02-01), Nakayama et al.
patent: 6880145 (2005-04-01), Wright et al.
patent: 2003/0237066 (2003-12-01), Ito

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