Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-22
2008-07-22
Lin, Sun J. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07404166
ABSTRACT:
The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
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Andreev Alexander E.
Nikitin Andrey A.
Panteleev Pavel
Lin Sun J.
LSI Corporation
Suiter Swantz pc llo
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