Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2005-09-27
2005-09-27
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S119000, C710S240000, C710S242000
Reexamination Certificate
active
06950892
ABSTRACT:
A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.
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Bell, Jr. Robert H.
Cargnoni Robert Alan
Cerullo Jeremy S.
Harris Andrew M.
Myers Paul R.
Salys Casimer K.
Weiss, Moy & Harris P.C.
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