Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-08-19
2000-10-31
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711133, 711135, 711159, 711160, G06F 1200
Patent
active
061417319
ABSTRACT:
Disclosed is a cache management scheme using multiple data structure. A first and second data structures, such as linked lists, indicate data entries in a cache. Each data structure has a most recently used (MRU) entry, a least recently used (LRU) entry, and a time value associated with each data entry indicating a time the data entry was indicated as added to the MRU entry of the data structure. A processing unit receives a new data entry. In response, the processing unit processes the first and second data structures to determine a LRU data entry in each data structure and selects from the determined LRU data entries the LRU data entry that is the least recently used. The processing unit then demotes the selected LRU data entry from the cache and data structure including the selected data entry. The processing unit adds the new data entry to the cache and indicates the new data entry as located at the MRU entry of one of the first and second data structures.
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Beardsley Brent Cameron
Benhase Michael Thomas
Martin Douglas A.
Morton Robert Louis
Reid Mark A.
Cabeca John W.
International Business Machines - Corporation
Peugh Brian R.
Victor David W.
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