Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-05-11
2002-11-19
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S309000
Reexamination Certificate
active
06484225
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to data processing within information processing systems. More particularly, this invention relates to inter-device communication within a computer system.
2. Description of the Related Art
Information processing systems, such as personal computers (PCs), have virtually become an inseparable part of many people's daily activities. These systems process an enormous amount of information in a relatively short time. To perform these sophisticated tasks, a computer system typically includes a central processor, memory modules, various system and bus control units, and a wide variety of peripheral data input/output (I/O) and storage devices. These computer components communicate using control and data signals having various data rates and signal protocols over multiple system buses.
Examples of such system buses include a peripheral component interconnect (“PCI”) bus, a scaleable coherent interface (“SCI”) bus, and a high performance parallel interface (“HIPPI”) bus. The PCI bus is a 32-bit or 64-bit bus with multiplexed address and data lines. The bus is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory devices. In some applications, the SCI bus uses point-to-point links and a packet protocol to support 64-bit physical addresses. The upper 16 bits of the 64-bit address specify a node number and the lower 48 bits of the 64-bit address specify an offset address. The SCI bus uses coaxial cables over medium distances (e.g., 10's of meters) and fiber optics over long distances (e.g., 10 km) to provide unidirectional point-to-point signaling, from a transmitting device (i.e., transmitter) to a receiving device (i.e., receiver), to simulate a bus. The SCI bus supports read and write transactions among the various devices within a computer system. A transaction includes request and response subactions. The request subaction transfers an address and a command (read or write), whereas the response subaction returns status. For a write transaction, data are included within the request packet. For a read transaction, data are included within the response packet. For a compound transaction (e.g., fetch and add), data are included within the request and response packets.
The HIPPI protocol supports bus communication over a simplex channel (point-to-point link) for transferring data in one direction. In some applications, the HIPPI bus uses a parallel data path to provide communication at 800 Mbps with a 32-bit data bus, and 1.6 Gbps with a 64-bit data bus. The HIPPI bus performs data transfers and flow control in increments of bursts, with each burst nominally containing 256 words (i.e., 1024 or 2048 bytes). The HIPPI bus provides error detection by using byte parity on the data bus, and immediately following each burst of data with a length/longitudinal redundancy checkword (LLRC). HIPPI framing protocol (FP) defines the framing for packets that will be sent over a HIPPI connection. Basically the HIPPI-FP standard splits a packet in three areas: Header_Area, D1_Area, and D2_Area. Each of these areas starts and ends on a 64-bit boundary. The Header_Area defines the sizes and offsets of the D1_Area and D2_Area. The D1_Area contains control information and the D2_Area contains data associated with the control information.
Despite the transfer power of these communication protocols, data and control traffic among computer devices is still prevalent. Bottlenecks of data and control traffic among central processing units (“CPUs”), memory devices, and external media all adversely affect processing speeds and efficiency rates of computer systems. Data and control transactions are often limited to a common path used by all devices in the system. For instance, data traffic for devices on various input/output (“I/O”) buses travels through the host processor bus. Additionally, all communications among peer devices travel through the host processor bus. Peer devices on the PCI bus may include one or more of the following: an audio card, a motion video card, a small computer system interface (SCSI) card, a graphics card, or other PCI—PCI bridges. For each transaction, a peer device may issue one or more interrupts to the processor to communicate to another device in the system. The frequency of interrupts results in unnecessary and often excessive data traffic on the host processor bus. More importantly, the involvement of the CPU in the management of these transactions slows computer processing speeds significantly.
Several attempts have been made in the field to resolve the bottleneck of traffic resulting from the above-described common path. Some of these attempts include employing data paths having higher data rate capacity, or widening data path bandwidths to support higher data throughput on the bus. These solutions, however, are often costly and, more importantly, limited by the capacity of the employed data path. Therefore, there is a need in the computer technology to manage device interrupts more effectively. The solution should provide a more efficient utility of CPUs while continuing to meet the demands of increasing control and data traffic.
SUMMARY OF THE INVENTION
To overcome the limitations of the related art, the invention provides a method of posting data and interrupt transactions for devices and local subsystems in a computer system. A local subsystem may include one or more peer devices. The invention provides a fabric controller, a concurrent bridge, and an interrupt controller to alleviate the need of burdening the CPU with every transaction in the system. Accordingly, unnecessary control and data flow through the host processor bus is minimized.
REFERENCES:
patent: 4449182 (1984-05-01), Rubinson et al.
patent: 4835737 (1989-05-01), Herrig et al.
patent: 4949245 (1990-08-01), Martin et al.
patent: 4968977 (1990-11-01), Chinnaswamy et al.
patent: 4999787 (1991-03-01), McNally et al.
patent: 5210855 (1993-05-01), Bartol
patent: 5265098 (1993-11-01), Mattson et al.
patent: 5269011 (1993-12-01), Yanai et al.
patent: 5272584 (1993-12-01), Austruy et al.
patent: 5317693 (1994-05-01), Cuenod et al.
patent: 5317747 (1994-05-01), Mochida et al.
patent: 5329625 (1994-07-01), Kannan et al.
patent: 5337413 (1994-08-01), Lui et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5357614 (1994-10-01), Pattisam et al.
patent: 5386567 (1995-01-01), Lien et al.
patent: 5426740 (1995-06-01), Bennett
patent: 5446910 (1995-08-01), Kennedy et al.
patent: 5471634 (1995-11-01), Giorgio et al.
patent: 5483419 (1996-01-01), Kaczeus, Sr. et al.
patent: 5493574 (1996-02-01), McKinley
patent: 5493666 (1996-02-01), Fitch
patent: 5517646 (1996-05-01), Piccirillo et al.
patent: 5530810 (1996-06-01), Bowman
patent: 5539913 (1996-07-01), Furuta et al.
patent: 5555510 (1996-09-01), Verseput et al.
patent: 5564024 (1996-10-01), Pemberton
patent: 5568610 (1996-10-01), Brown
patent: 5579491 (1996-11-01), Jeffries et al.
patent: 5581712 (1996-12-01), Herrman
patent: 5586250 (1996-12-01), Carbonneau et al.
patent: 5588121 (1996-12-01), Reddin et al.
patent: 5588144 (1996-12-01), Inoue et al.
patent: 5606672 (1997-02-01), Wade
patent: 5608876 (1997-03-01), Cohen et al.
patent: 5615207 (1997-03-01), Gephardt et al.
patent: 5632021 (1997-05-01), Jennings et al.
patent: 5638289 (1997-06-01), Yamada et al.
patent: 5644470 (1997-07-01), Benedict et al.
patent: 5644731 (1997-07-01), Liencres et al.
patent: 5651006 (1997-07-01), Fujino et al.
patent: 5652832 (1997-07-01), Kane et al.
patent: 5664119 (1997-09-01), Jeffries et al.
patent: 5680288 (1997-10-01), Carey et al.
patent: 5696970 (1997-12-01), Sandage et al.
patent: 5721935 (1998-02-01), DeSchepper et al.
patent: 5726506 (1998-03-01), Wood
patent: 5740378 (1998-04-01), Rehl et al.
patent: 5747889 (1998-05-01), Raynham et al.
patent: 5748426 (1998-05-01), Bedingfield et al.
patent: 5754797 (1998-05-01), Takahashi
patent: 5761033 (1998-06-01), Wilhelm
patent: 5761045 (1998
Sheikh Tahir Q.
Wallach Walter A.
Auve Glenn A.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
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