Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2007-08-21
2007-08-21
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S500000, C713S501000
Reexamination Certificate
active
10741319
ABSTRACT:
A method of maintaining a count of active events of a process is provided by a start counter and a complete counter. The start counter maintains a first count of start events and may be operated upon only by the start event of the process. The complete counter maintains a second count of complete events and may be operated upon only by the complete event of the process. The count of active events is established by determining the difference between the first and second counts. The present invention further provides for re-setting the first and second counts of the start and complete counters, respectively, when one or both of the counters have reached a maximum count value.
REFERENCES:
patent: 4140087 (1979-02-01), Daumer et al.
patent: 5263361 (1993-11-01), Gates
patent: 6631167 (2003-10-01), Cambonie et al.
patent: 6940516 (2005-09-01), Dotson
patent: 2004/0208383 (2004-10-01), Bossen
Cao Chun
Cribbs Malcolm D
LSI Corporation
Suiter Swantz PC LLO
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